Semiconductor Voltage Segmentation for High-Speed Data Transfer
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Solution Overview
Problem
The reduction of internal operation voltage in semiconductor devices, such as DRAM, leads to increased ON-resistance of column switches and slower charge movement, making high-speed data transfer and word line operation challenging due to the large difference between internal and external voltages.
Innovation Solution
Incorporating input buffers and level shifters that convert address signals from external voltage VDD to internal operation voltage VPERI and vice versa, ensuring high-speed data transfer and rapid word line operations by reducing ON-resistance and optimizing voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal operation voltage VPERI is reduced to enable downscaling, then energy consumption is reduced, but the ON-resistance of column switches increases and charge movement becomes slow
Solution Approach 1:
The patent segments the voltage supply into multiple internal operation voltages (VPERI for peripheral circuits and VARY for array-system circuits) rather than using a single voltage. This allows different parts of the semiconductor device to operate at different voltage levels optimized for their specific functions, enabling low voltage operation for energy efficiency while maintaining high-speed operation for performance-critical components.
Solution Approach 2:
Different regions of the semiconductor device are assigned different operation voltages based on their specific requirements. The peripheral circuits use VPERI while the array-system circuits use VARY, allowing each region to operate at the optimal voltage for its function. This local quality approach resolves the contradiction by enabling low voltage operation in energy-sensitive areas while maintaining high voltage in performance-critical areas.
2Use of energy by moving object
If the internal operation voltage VPERI is reduced, then power consumption decreases, but data transfer speed between bit line pair and IO line pair decreases
Solution Approach 1:
The patent divides the device into separate voltage domains (VPERI for peripheral circuits and VARY for array-system circuits), allowing data transfer operations to occur at the higher VARY voltage level while the overall device operates at lower VPERI voltage for energy efficiency. This segmentation enables high-speed data transfer without proportionally increasing overall power consumption.
Solution Approach 2:
The patent changes the operating voltage parameter dynamically based on the operational mode. During data transfer operations, the array-system circuits operate at VARY which is higher than VPERI, thereby maintaining high data transfer speed. The system switches between different voltage parameters to optimize both power consumption and performance as needed.
3Use of energy by moving object
If the internal operation voltage VPERI is reduced, then energy efficiency improves, but word line operation speed decreases due to large voltage difference between VPERI and VPP
Solution Approach 1:
The patent segments the voltage supply into VPERI for peripheral circuits and introduces VARY specifically for array-system circuits including word line operations. This segmentation allows word line operations to use VARY which has a smaller difference from VPP compared to using VPERI directly, thereby reducing the voltage conversion time and improving word line operation speed while maintaining overall energy efficiency through low VPERI operation.
Solution Approach 2:
The array-system circuits are assigned a dedicated voltage VARY that is optimized for their specific operation requirements. Since VARY is closer to VPP than VPERI is, this local quality approach reduces the voltage difference and enables faster word line operations in the array region while the rest of the device operates at the lower VPERI voltage for energy efficiency.
Data Source
AI summary
A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude.