Semiconductor Device Data Reference Voltage Sensing

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Solution Overview

Problem

In semiconductor devices, accurately sensing parameters such as the time for a data reference voltage to reach a target level is challenging due to capacitive and loading effects from monitoring pads and sensing equipment, especially at high operating frequencies.

Innovation Solution

A semiconductor device with a data storage unit, test operation unit, and test operation sensing signal generation unit that generates and compares test data and comparison data to determine the logic level of the data reference voltage, allowing for precise sensing of the time taken for the voltage to reach a target level, even at high frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the data reference voltage is sensed outside the semiconductor device using monitoring pads and sensing equipment, then the training test can be performed, but the measurement accuracy deteriorates due to capacitive and loading effects

Engineering Contradiction:
Improvemeasurement accuracyVSAvoidcapacitive and loading effects
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the sensing operation from the external environment (monitoring pads and sensing equipment) and relocates it inside the semiconductor device. By generating the test operation sensing signal within the device boundaries, the measurement process is isolated from external capacitive and loading effects, thereby resolving the contradiction between performability and measurement accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary mechanism (the test operation sensing signal generation unit) that mediates between the data reference voltage generation and the external sensing equipment. This intermediary generates internal sensing signals that are immune to external effects, allowing accurate measurements without direct exposure to harmful external factors

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the operating frequency of the semiconductor device is increased to achieve high-speed operation, then the processing speed improves, but the sensing stability deteriorates

Engineering Contradiction:
Improveoperating frequencyVSAvoidsensing stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The patent performs preliminary action by generating the test operation sensing signal in advance based on test commands received before high-frequency operation begins. This pre-generated sensing signal provides a stable reference that remains valid during high-speed operation, resolving the contradiction between speed and sensing stability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action by generating test operation sensing signals at specific intervals based on test entry and exit commands. This periodic generation ensures that sensing operations are synchronized with the high-frequency operation cycles, maintaining stability even at elevated operating frequencies

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8659962B2Semiconductor device, semiconductor system having the same and operating method thereof
Publication Date: 2014.02.25 SK HYNIX INC
  • US8659962B2 patent drawing
  • US8659962B2 patent drawing
  • US8659962B2 patent drawing

AI summary

A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of test data periodically in response to a data reference voltage whose voltage level is determined in response to a level test code during a test operation period defined by a test entry command and a test exit command, and generate a test result signal by comparing a logic level of the comparison data with the logic level of the test data; and a test operation sensing signal generation unit configured to generate a test operation sensing signal that is activated in response to the test entry command and inactivated in response to the test result signal.