Semiconductor Package Wafer Bonding to Prevent Upper Wafer Peeling

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Solution Overview

Problem

The challenge in semiconductor packaging is preventing the upper wafer from peeling off due to the absence of a molding layer between the semiconductor chip and the upper layer, which is critical for maintaining package integrity and functionality as devices become smaller and more complex.

Innovation Solution

A method is developed where an adhesive layer is formed between the semiconductor chip and the upper wafer, and a molding layer is formed between the lower and upper wafers to surround the adhesive layer, ensuring the upper wafer is securely bonded and preventing peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are integrated into a single package to reduce size, then package capacity and functionality are improved, but the risk of wafer peeling increases due to absent molding layer support

Engineering Contradiction:
Improvepackage capacityVSAvoidwafer bonding stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces an adhesive layer as an intermediary substance between the semiconductor chip and the upper wafer to provide bonding support in the absence of a molding layer. This adhesive layer acts as a mediator that compensates for the missing structural support, preventing wafer peeling while enabling multiple chip integration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the bonding interface parameters by changing from direct wafer-to-chip bonding to adhesive-layer-mediated bonding. This parameter change in the bonding mechanism allows for secure attachment of multiple chips without requiring a molding layer, thus maintaining reliability while achieving high package capacity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If adhesive layer width is increased beyond chip width to ensure bonding coverage, then bonding reliability is improved, but material usage and process complexity increase

Engineering Contradiction:
Improvebonding reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The adhesive layer is prepared and positioned in advance with a predetermined width greater than the chip width before the bonding process. This preliminary preparation ensures adequate bonding coverage and reliability without requiring complex real-time adjustments during assembly, thus managing process complexity while maintaining high bonding reliability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents the upper wafer from peeling off, enhancing the structural integrity and functionality of semiconductor packages by ensuring a secure bonding process, even in compact and high-capacity designs.

Implementation Method 1

forming an adhesive layer between a semiconductor chip and the upper wafer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer

Methodology Applied
Scientific EffectBonding: Welding

Data Source

PatentUS20240030176A1Method of fabricating semiconductor package
Publication Date: 2024.01.25 SAMSUNG ELECTRONICS CO LTD
  • US20240030176A1 patent drawing
  • US20240030176A1 patent drawing
  • US20240030176A1 patent drawing

AI summary

A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.