Semiconductor Wafer Bonding with Recessed Electrodes and Interlayer
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing bonding strength and conductivity between wafers, particularly due to void generation and reduced bonding area during the bonding process of stacked modules.
Innovation Solution
The semiconductor device incorporates a first and second wafer with specific electrode configurations, including recessed portions and interlayer structures, where a conductive first layer is positioned between the electrodes and insulating layers to manage stress and ensure adequate bonding area, thereby preventing voids and enhancing conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafers are bonded to form stacked modules, then integration density and functionality are improved, but void generation and reduced bonding area occur leading to weakened bonding strength
Solution Approach 1:
The patent applies preliminary action by forming recessed portions in the electrodes before the bonding process. These recesses are prepared in advance to accommodate void formation during bonding, preventing voids from reducing the effective bonding area. The conductive layer is also formed preliminarily within these recessed portions to maintain electrical connectivity despite the presence of voids.
Solution Approach 2:
The patent introduces a conductive layer as an intermediary substance within the recessed portions of the electrodes. This conductive layer fills the space that would otherwise be occupied by voids, maintaining both mechanical bonding strength and electrical conductivity. The intermediary conductive material allows the structure to accommodate bonding imperfections while preserving functionality.
2Strength
If electrodes are formed with larger area to improve bonding strength, then bonding area is improved, but stress concentration and void formation increase
Solution Approach 1:
The patent segments the electrode structure by forming recessed portions within the electrode body. This segmentation creates a hierarchical structure where the overall electrode maintains large area for bonding strength, while the recessed portions distribute and accommodate void formation locally, preventing voids from compromising the entire bonding interface.
Solution Approach 2:
The patent introduces a vertical dimension to the electrode structure by forming recessed portions that extend into the electrode body. This dimensional change allows the electrode to maintain large planar area for bonding while creating internal volume to accommodate voids, effectively separating the bonding function from the void-prone regions.
3Reliability
If conductive layers are added to maintain conductivity in void regions, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The conductive layer formed in the recessed portions serves multiple functions simultaneously: it maintains electrical connectivity through void regions, provides mechanical support to the bonding interface, and prevents void formation from compromising bonding strength. This multi-functionality reduces the need for additional separate structures to address each issue independently.
Solution Approach 2:
The patent merges the void accommodation function and the electrical connectivity function into a single integrated structure. The recessed portions and conductive layers are formed as part of the electrode fabrication process itself, combining structural and electrical functions rather than requiring separate components for each function.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.