Semiconductor Wafer Concurrent Die Testing via Shared Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for testing integrated circuits on semiconductor wafers are slow and becoming increasingly complex due to the increasing number of bond pads and smaller probe pads, leading to higher costs as more probe pins and tester channels are required.
Innovation Solution
The solution involves forming a non-uniform array of integrated circuits on a semiconductor wafer with common electrical interconnects that couple probe pads across adjacent dies, allowing for concurrent testing using fewer probes by connecting probe pads in series and using a common electrical interconnect to supply input test patterns to all dies simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more probe pins and tester channels are added to test more dies in parallel, then testing speed increases, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple probe pads from different dies into a single shared probe pad through common electrical interconnects. Multiple dies share common interconnects that connect to a single probe pad, allowing parallel testing of multiple dies using fewer physical probes. This combining approach increases testing throughput while reducing the number of required probe pins and tester channels.
Solution Approach 2:
The common electrical interconnects serve multiple functions: they electrically connect multiple probe pads across adjacent dies, provide shared test signal distribution, and enable parallel testing of multiple dies through a single probe interface. This multi-functionality allows the testing system to handle more dies with the same number of probes, improving productivity without increasing device complexity.
2Adaptability or versatility
If the number of die bond pads increases and probe pads get smaller, then circuit functionality increases, but testing complexity and cost increase
Solution Approach 1:
The patent combines multiple small probe pads into a single shared probe pad through common electrical interconnects. By merging the electrical connections of multiple probe pads, the system can test more circuits with the same physical probe resources, reducing testing complexity despite increased circuit functionality and more bond pads.
Solution Approach 2:
The patent extends electrical interconnects across die boundaries into the array boundary region, utilizing the spatial dimension between dies. This cross-die interconnection approach allows probe pads on adjacent dies to be electrically coupled through the array boundary region, enabling shared probing without increasing probe pad size or complexity.
3Measurement precision
If probe testing is performed serially on each die, then testing accuracy is maintained, but testing time increases
Solution Approach 1:
The patent merges multiple testing operations into a single parallel testing operation by electrically coupling probe pads across adjacent dies through common interconnects. Multiple dies are tested simultaneously using shared probes and common interconnects, dramatically reducing total testing time while maintaining testing accuracy through proper signal distribution and isolation.
Solution Approach 2:
The patent performs preliminary electrical coupling of probe pads through common interconnects before the actual testing process. The test structure with shared interconnects is prepared in advance, allowing multiple dies to be tested in parallel from the start, eliminating the need for sequential probe movement and reducing overall testing time.
Data Source
AI summary
A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.