3D Topographical Defect Classification on Patterned Semiconductor Wafers
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Solution Overview
Problem
Current automated defect classification techniques in the semiconductor industry face challenges in accurately identifying and classifying defects on patterned wafers, particularly in distinguishing between defects and process variations, due to limitations in capturing and analyzing three-dimensional topographical and contextual attributes.
Innovation Solution
The proposed system utilizes a scanning electron microscope (SEM) to generate 3D maps of semiconductor wafers, computes 3D shape and texture parameters, and integrates computer-aided design (CAD) data to classify defects based on context attributes, such as overlap, bridging, and proximity to pattern elements, enabling more precise defect characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional 2D image-based defect classification is used, then the system complexity is low, but the measurement precision and classification accuracy are insufficient
Solution Approach 1:
The patent transitions from 2D image-based defect analysis to 3D topographical analysis by generating height maps and calculating three-dimensional shape parameters (area, perimeter, circularity, aspect ratio, solidity). This dimensional enhancement provides richer defect characteristics for more accurate classification while maintaining computational feasibility through automated parameter extraction.
2Measurement precision
If 3D mapping techniques are implemented, then the measurement precision is improved, but the use of energy and processing time increase
Solution Approach 1:
The system performs preliminary 3D mapping and topographical analysis during the initial inspection phase, generating height maps and shape parameters in advance. This preliminary action enables subsequent defect classification to use pre-computed 3D features without requiring additional energy-intensive processing during the classification stage, thus reducing overall energy consumption while maintaining measurement precision.
3Measurement precision
If more defect attributes are analyzed, then the classification accuracy is improved, but the loss of time in processing increases
Solution Approach 1:
The patent segments the defect analysis process into distinct computational steps: 3D height map generation, shape parameter calculation (area, perimeter, circularity, aspect ratio, solidity), and classification decision-making. This segmentation allows for optimized processing of each attribute type and enables selective computation of only the most discriminative features for each defect type, reducing overall processing time while maintaining high classification accuracy.
4Productivity
If automated defect classification is implemented, then the productivity is improved, but the reliability may be reduced due to difficulty in detecting subtle defects
Solution Approach 1:
The patent transforms defect detection from qualitative visual inspection to quantitative 3D parameter measurement by calculating precise shape parameters (area, perimeter, circularity, aspect ratio, solidity) from height maps. This parameter transformation enables automated classification systems to reliably detect and characterize subtle defects that may be difficult for human inspectors to identify, thereby maintaining high reliability while improving productivity through automation.
Data Source
AI summary
A method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing a location of interest. At least one value for one or more attributes of the location of interest are computed based upon topographical features of the location of interest in a three-dimensional (3D) map of the area.