Semiconductor Wafer Dicing Method to Suppress Chip Cracking
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Solution Overview
Problem
The challenge is to reduce the thickness of semiconductor wafers to 80 μm or less for chip production without causing chip cracking during the dicing process, as existing methods do not provide a concrete technique for achieving thin-type semiconductor chips with reduced cracking.
Innovation Solution
A method involving a specific dicing process where the blade is advanced along the crystal orientation of the semiconductor wafer, reducing stress and cracking by cutting along the X and Y directions, and using a combination of thick and thin semiconductor chips in alternating tiers to absorb unevenness and enhance adhesive strength, along with a reverse bonding wire method to minimize chip fracture during resin molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of semiconductor wafer is reduced to 80 μm or less, then the thickness of semiconductor device is reduced, but chip cracking occurs during dicing
Solution Approach 1:
The patent applies preliminary action by performing dicing before thinning the semiconductor wafer. The wafer is diced at its original thicker state where it has sufficient mechanical strength to withstand the cutting process, and then thinned to the target thickness of 80 μm or less. This sequence prevents chip cracking during dicing while achieving the desired thin final product.
Solution Approach 2:
The patent changes the parameter sequence of the manufacturing process. Instead of thinning first then dicing (which causes cracking), it reverses the parameter change sequence by dicing first at thicker state, then thinning to achieve the final thin specification. This parameter reordering resolves the contradiction between achieving thinness and preventing cracking.
2Quantity of substance
If multiple semiconductor chips are laminated in multiple tiers, then the capacity of semiconductor device is increased, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the manufacturing process into distinct stages: wafer preparation, dicing, thinning, and lamination. Each stage handles a specific task independently, making the complex multi-tier manufacturing process more manageable and controllable, thereby reducing overall manufacturing complexity while enabling increased chip quantity.
Solution Approach 2:
The patent utilizes the vertical dimension by laminating semiconductor chips in multiple tiers stacked vertically. This three-dimensional arrangement increases the quantity of chips per device without expanding the planar footprint, and the standardized lamination process manages the complexity of integrating multiple layers.
Data Source
AI summary
Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.