Semiconductor Wafer Dicing via Laser Grooving and Blade Sawing
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Solution Overview
Problem
The existing semiconductor wafer dicing processes face challenges such as cracking and chipping due to stress and thermal expansion during the sawing operation, especially when dealing with low-k dielectric materials, which affect the reliability of the semiconductor chips.
Innovation Solution
The proposed solution involves performing multiple laser grooving operations followed by blade saw operations to reduce stress and prevent cracking, with specific laser beam profiles and dual laser beams used to selectively remove metal pads and passivate surfaces, and for non-low-k materials, a dual laser grooving operation is conducted before blade sawing to minimize thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of stationary object
If the wafer thickness is reduced by grinding to form thin packages, then the package weight and thickness are reduced, but the area-to-thickness ratio increases tremendously causing cracks during transportation and tape attachment
Solution Approach 1:
The patent applies laser grooving before the blade sawing operation to pre-weaken the material along the desired cut path. This preliminary action creates a controlled fracture path that guides the subsequent mechanical cutting, preventing uncontrolled cracking during the dicing process while maintaining the thinned wafer structure
Solution Approach 2:
The patent replaces part of the mechanical cutting process with laser grooving. Instead of relying solely on mechanical blade sawing which causes stress and cracking in thinned wafers, the laser grooving creates a controlled fracture path that reduces the mechanical stress during the subsequent cutting operation
2Productivity
If blade sawing is performed on thinned wafers, then the silicon chips are separated for packaging, but stress during sawing produces cracks on the top surface adjacent to the kerfs
Solution Approach 1:
The laser grooving operation is performed before blade sawing to pre-create a fracture path along the kerf line. This preliminary action allows the subsequent mechanical cutting to proceed with minimal stress on the thinned wafer, preventing cracks on the top surface while maintaining efficient chip separation
Solution Approach 2:
The dicing process is segmented into two distinct operations: laser grooving to create the fracture path, and blade sawing to complete the separation. This segmentation allows each operation to be optimized independently, with laser grooving handling the stress-sensitive thinned wafer and blade sawing providing the final clean separation
3Reliability
If multiple laser grooving operations are performed followed by blade sawing, then crack and chipping rates are reduced to ultra-low levels, but the process complexity increases
Solution Approach 1:
The laser grooving operations are performed as preliminary steps before blade sawing to pre-create the fracture path and reduce stress during mechanical cutting. This preliminary action significantly reduces crack and chipping rates by controlling where and how the material fractures during the subsequent sawing operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces crack and chipping rates to ultra-low levels (approximately 0 ppm and <500 ppm), enhancing the reliability and production efficiency of semiconductor wafers by minimizing mechanical and thermal stress during the dicing process.
Implementation Method 1
forming a first trench by applying a laser beam along an inactive region of the wafer to remove a first portion of the inactive region
Data Source
AI summary
A semiconductor chip structure includes a substrate having a top surface, a bottom surface, and a lateral surface connecting the top surface and the bottom surface. The lateral surface includes a first portion having a first surface roughness and being in proximity to the top surface, and a second portion having a second surface roughness and being in proximity to the bottom surface. The first surface roughness is greater than the second surface roughness. A method for manufacturing the semiconductor chip structure is also provided.