Semiconductor Wafer Metallization Using Dissolvable Self-Aligned Mask
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in achieving smooth and precise metallization of the back surfaces of semiconductor chip regions during the wafer-level singulation, leading to surface roughness issues that affect the electrical connections and overall performance of the semiconductor devices.
Innovation Solution
A method involving the use of selectively dissolvable material layers with different solubility parameters is applied to create a self-aligned mask for metal deposition, ensuring smooth side walls with average surface roughness less than 100 nm, facilitating precise metallization and electrical contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metallization processes are used on wafer back surfaces, then electrical connections can be established, but surface roughness exceeds 100 nm resulting in poor connection quality
Solution Approach 1:
A dissolvable support structure is applied to the wafer back surface before metallization. This preliminary action creates a self-aligned mask that defines the metallization pattern and provides a smooth template for metal deposition, ensuring surface roughness remains below 100 nm while enabling reliable electrical connections.
Solution Approach 2:
The dissolvable support structure acts as an intermediary element during the metallization process. It serves as a temporary mask and smoothing layer that is removed after metallization, leaving behind a precise metal pattern with smooth surfaces. This intermediary structure resolves the contradiction by enabling both precise patterning and surface smoothness.
2Productivity
If wafer-level singulation is performed without self-aligned masking, then manufacturing efficiency is maintained, but metallization precision and side wall smoothness deteriorate
Solution Approach 1:
The dissolvable support structure is applied in a self-aligned manner, where the mask pattern is automatically registered with the wafer features. This self-alignment eliminates the need for complex alignment steps during wafer-level processing, maintaining high productivity while achieving precise metallization patterns with smooth side walls.
3Ease of manufacture
If traditional dicing and metallization steps are used, then device fabrication can be completed, but surface roughness and connection reliability are compromised
Solution Approach 1:
The patent combines the masking function and the smoothing function into a single dissolvable support structure layer. This merged structure serves both as a pattern definition mask and as a surface-smoothing template during metallization, simplifying the fabrication process while ensuring electrical contact smoothness remains below 100 nm surface roughness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor components with smooth electrical contact layers, enhancing the electrical connections and reducing surface roughness, thereby improving the performance and reliability of the semiconductor devices.
Implementation Method 1
The dissolvable support structure is removed by a dissolving agent
Implementation Method 2
metal layers are formed on the semiconductor chip regions with side walls having a smooth surface
Data Source
AI summary
A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.