Semiconductor Wafer With Dual Crystallographic Orientations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor wafers face challenges in achieving high-frequency operations and low power consumption while preventing malfunctions due to undesired current paths, particularly in balancing the mobility differences between electrons and holes in NMOS and PMOS transistors.
Innovation Solution
A semiconductor wafer with a semiconductor layer formed on an insulation film, featuring regions with different crystallographic orientations (100) and (110), allowing for enhanced mobility of charge carriers, where the (100) orientation is used for NMOS transistors and the (110) orientation for PMOS transistors, enabling improved performance and reduced leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single crystallographic orientation is used for the semiconductor substrate, then the manufacturing process is simple, but the mobility of charge carriers is compromised for both NMOS and PMOS transistors
Solution Approach 1:
The semiconductor substrate is divided into first and second regions with different crystallographic orientations. The first region has a first crystallographic orientation optimized for NMOS transistors, while the second region has a second crystallographic orientation optimized for PMOS transistors. This local differentiation allows each region to provide high charge carrier mobility for its specific transistor type, resolving the contradiction between manufacturing simplicity and charge carrier mobility.
2Reliability
If the PMOS transistor is designed with a wider channel width to compensate for lower hole mobility in (100) orientation, then the mobility compensation is achieved, but the device area increases
Solution Approach 1:
Instead of increasing the channel width of PMOS transistors to compensate for lower hole mobility, the invention provides a second region with a second crystallographic orientation specifically optimized for PMOS transistors. This allows PMOS transistors to achieve high hole mobility without requiring increased device area, thus resolving the contradiction between mobility compensation and area minimization.
3Speed
If high-frequency operation is achieved through optimized crystallographic orientation, then operational speed improves, but the device complexity increases due to multiple orientation regions
Solution Approach 1:
The substrate is divided into first and second regions with different crystallographic orientations, where each region is optimized for specific transistor types. This local optimization enables high-frequency operation by providing the appropriate crystallographic orientation for each transistor type, achieving high speed while managing complexity through functional zoning rather than uniform complex structures.
Solution Approach 2:
The semiconductor substrate is segmented into distinct first and second regions with different crystallographic orientations. This segmentation allows each region to be optimized independently for its specific transistor type, enabling high-frequency operation while maintaining manageable overall device complexity through clear functional division.
Data Source
AI summary
Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.