Semiconductor Wafer Insulative Layer Deposition
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Solution Overview
Problem
The formation of bond pad regions on semiconductor wafers is challenging due to plating on the back side, which wastes materials and compromises circuit performance, and the need for flipping the wafer during insulative layer formation leads to defects and additional process steps, including high-temperature annealing of passivation layers.
Innovation Solution
Simultaneous deposition of insulative material, such as silicon nitride, across both the front and back sides of the semiconductor wafer using plasma-enhanced atomic layer deposition (PEALD), eliminating the need for wafer flipping and allowing thermal treatment of passivation layers during deposition, thereby reducing process steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor construction is flipped to form an insulative layer on the back side, then plating on the back side is prevented, but abrasions or defects occur during flipping
Solution Approach 1:
An insulative layer is deposited on the back side surface before the plating process. This preliminary action prevents plating material from depositing on the back side during subsequent processing, eliminating the need to flip the wafer and avoiding the associated defects.
2Reliability
If the semiconductor construction is flipped to form an insulative layer on the back side, then plating on the back side is prevented, but additional process steps are required
Solution Approach 1:
The formation of the insulative layer on the back side is combined with the existing front side processing sequence. The insulative layer is deposited as part of the overall fabrication process rather than as a separate, additional step, thereby reducing process complexity.
3Reliability
If high-temperature annealing is performed to treat the passivation layer, then hydrogen migration is promoted, but process throughput is reduced
Solution Approach 1:
The high-temperature annealing process for hydrogen migration is merged with the insulative layer deposition process. Both processes are performed simultaneously in the same equipment, eliminating the need for separate processing steps and improving overall throughput.
4Reliability
If high-temperature annealing is performed separately to treat the passivation layer, then proper thermal treatment is achieved, but process cost increases
Solution Approach 1:
The annealing process and insulative layer deposition are combined into a single process step. This consolidation reduces the total number of process steps, decreases equipment usage time, and lowers overall manufacturing costs while still achieving the required thermal treatment of the passivation layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents back-side plating, reduces defects, and consolidates process steps, improving throughput and reducing costs by allowing thermal treatment of passivation layers without additional steps, while maintaining the integrity of the semiconductor construction.
Implementation Method 1
Simultaneous deposition of insulative material, such as silicon nitride, across both the front and back sides of the semiconductor wafer using plasma-enhanced atomic layer deposition (PEALD)
Implementation Method 2
Such temperature may be at least about 400° C. The anneal adds an additional process step. As each additional process step reduces throughput, creates risk of error, and increases cost; it is desired to reduce the number of process steps.
Data Source
AI summary
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.