Semiconductor Wafer Process Control Monitor Placement
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Solution Overview
Problem
Conventional semiconductor manufacturing techniques fail to effectively analyze defects on the rear surface of semiconductor wafers, particularly in reverse conducting-IGBTs, due to the absence of process control monitors (PCMs) on this surface, making it difficult to identify the cause of defects and variations.
Innovation Solution
A method of manufacturing semiconductor devices that includes forming process control monitors (PCMs) on both the front and rear surfaces of the semiconductor wafer, allowing for concurrent ion implantation and evaluation of active regions, enabling comprehensive analysis of manufacturing processes and defect identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PCMs are only formed on the front surface of the semiconductor wafer, then the manufacturing process is simpler and fewer resources are used, but the ability to analyze defects and identify cause on the rear surface is insufficient
Solution Approach 1:
The patent applies dimensionality change by extending PCM formation from the traditional single front-surface location to both front and rear surfaces of the semiconductor wafer. This spatial expansion enables comprehensive defect analysis on both surfaces, allowing identification of defects that occur during rear-surface processing without adding significant complexity to the overall manufacturing system.
2Reliability
If PCMs are formed on both front and rear surfaces, then comprehensive defect analysis is enabled, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent merges the PCM formation process with the existing ion implantation process for creating active regions. By using the same ion implantation equipment and methodology to form both the active regions in chip areas and the PCMs in non-chip areas, the manufacturing cycle time is minimized while achieving comprehensive defect analysis capability on both wafer surfaces.
Solution Approach 2:
The patent performs PCM formation on both surfaces during the same ion implantation step used for creating active regions, rather than adding separate subsequent steps. This preliminary integration of PCM formation into the existing process flow ensures that defect analysis capability is built in from the early stages of manufacturing, reducing overall process time and complexity.
3Manufacturing precision
If ion implantation is performed separately for active regions and PCMs, then precise control of each region is achieved, but the manufacturing process becomes more complex and less efficient
Solution Approach 1:
The patent makes the ion implantation process universal by using the same implantation step to accomplish multiple functions: forming active regions in chip areas and forming PCMs in non-chip areas on both front and rear surfaces. This multi-functional approach maintains precise control over dopant distribution while eliminating the need for separate implantation processes, thereby reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for thorough analysis of rear-surface manufacturing processes, facilitating the identification of defect causes and improving the reliability and yield of semiconductor devices by providing comprehensive evaluation of each layer and region.
Implementation Method 1
concurrent ion implantation to form the process control monitor and the active regions
Data Source
AI summary
A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.