Ultra-Thin Semiconductor Wafer Warpage Control

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Solution Overview

Problem

Thinning semiconductor wafers to improve power efficiency leads to warpage and cracking issues during transportation and fabrication due to mechanical stress, which affects the reliability of vertical power devices.

Innovation Solution

A manufacturing method for an ultra-thin semiconductor device package structure involves forming a patterned protecting layer, creating a trench in the channel portion, and using a supporting board to stabilize the wafer during thinning, followed by forming a conductive structure and back electrode layer to reduce warpage and enhance mechanical strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the wafer is thinned to improve power efficiency, then the resistance of vertical power devices is reduced, but the wafer becomes more prone to warpage and cracking

Engineering Contradiction:
Improvepower efficiencyVSAvoidwafer integrity
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The wafer thinning process is segmented into multiple stages: initial thinning to intermediate thickness, formation of supporting structures (trenches filled with conductive material or air gaps), and final thinning to ultra-thin thickness. This staged approach allows the wafer to maintain structural integrity during processing while achieving the target thickness for low resistance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Supporting structures are introduced as intermediary elements during the thinning process. These structures (trenches filled with conductive material or air gaps) provide mechanical support to the wafer during thinning and subsequent processing, preventing warpage and cracking while allowing the wafer to be thinned to ultra-thin dimensions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If the wafer is thinned to reduce current path length, then power efficiency is improved, but mechanical strength decreases

Engineering Contradiction:
Improvepower efficiencyVSAvoidmechanical strength
Core Design Contradiction:
Use of energy by moving objectVSStrength

Solution Approach 1:

The thinning process is divided into stages with intermediate supporting structures that provide mechanical strength during processing. Once the device is fabricated and tested, the supporting structures are removed to achieve the final ultra-thin configuration with reduced current path length and optimal power efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Supporting structures are formed preliminarily during the fabrication process to provide mechanical strength. These structures are removed after the device is fabricated and tested, leaving the ultra-thin wafer with optimized electrical characteristics

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If the wafer is thinned to achieve shorter current path, then resistance is reduced, but warpage occurs during processing

Engineering Contradiction:
Improvecurrent path lengthVSAvoidwafer flatness
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

Supporting structures (trenches filled with conductive material or air gaps) are introduced as intermediary elements that maintain wafer flatness during thinning and subsequent processing steps. These structures prevent warpage by providing mechanical support to the thinning wafer while allowing the current path to be optimized

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The wafer thickness parameter is changed in a controlled manner through staged thinning, with supporting structures maintaining flatness at each stage. This allows the current path length to be optimized while preventing warpage during processing

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9881897B2Manufacturing method of ultra-thin semiconductor device package assembly
Publication Date: 2018.01.30 NIKO SEMICON
  • US9881897B2 patent drawing
  • US9881897B2 patent drawing
  • US9881897B2 patent drawing

AI summary

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.