Non-Destructive Stress Mapping in Semiconductor Wafers with Through Vias
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Solution Overview
Problem
Conventional methods for determining mechanical stress in semiconductor wafers with vias require sawing the wafer, which alters the stress being measured, making it difficult to accurately assess the stress induced in semiconductor material wafers supporting interconnection levels.
Innovation Solution
A method involving the creation of a test structure from a second wafer with a similar via configuration, where mechanical stress is measured on a rear surface layer, and finite element simulations are used to deduce the stress in the original wafer, allowing for stress mapping without sawing the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement methods (micro-Raman spectroscopy, X-ray diffraction, DISC) are used to measure mechanical stress in semiconductor wafers, then stress measurement is possible, but the wafer must be sawn which alters the stress being measured, reducing measurement precision
Solution Approach 1:
A test structure is manufactured in advance on a separate test wafer before the actual measurement process. This test structure includes a rear surface layer with embedded measurement elements that are prepared beforehand, allowing stress measurement without needing to saw the production wafer. The preliminary preparation of measurement structures eliminates the destructive sawing step while maintaining measurement capability.
Solution Approach 2:
A test wafer serves as an intermediary between the measurement system and the production wafer. The test wafer contains a test structure that replicates the stress conditions of the production wafer, allowing indirect measurement of stress without directly interfering with the production wafer integrity. This intermediary approach enables non-destructive stress assessment.
2Difficulty of detecting and measuring
If the wafer is sawn to access regions for stress measurement, then measurement access is obtained, but the stress is released or modified, worsening the reliability of the measurement
Solution Approach 1:
The test structure is designed to be self-contained on the test wafer, with all necessary measurement elements integrated into the rear surface layer. The test structure itself provides the measurement capability without requiring external intervention that would compromise the production wafer. The measurement system interacts with the test structure's built-in elements rather than requiring wafer segmentation.
Solution Approach 2:
The measurement approach transitions from accessing stress through lateral segmentation (sawing the wafer into sections) to accessing stress through the vertical dimension (measuring through the rear surface layer). This dimensional shift allows measurement without disrupting the wafer's lateral integrity, preserving the original stress state while enabling measurement access.
3Measurement precision
If a test structure is manufactured on a separate test wafer with identical via formation, then non-destructive measurement is enabled, but the device complexity increases due to additional manufacturing steps
Solution Approach 1:
The test structure utilizes parameter variations in the rear surface layer (material composition, layer thickness, embedding depth of measurement elements) to enable stress measurement functionality. By changing these parameters in the test wafer while maintaining identical via formation processes, the test structure achieves measurement capability without requiring fundamental process deviations, thus limiting the increase in manufacturing complexity.
Solution Approach 2:
The test structure is created as a copy of the production wafer's via structure on a separate test wafer. This copying approach allows the test wafer to replicate the stress conditions of the production wafer using identical via formation methods, while the added rear surface layer provides measurement capability. The copying strategy minimizes complexity by reusing proven process steps rather than developing entirely new manufacturing approaches.
Data Source
AI summary
A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.