Semiconductor Device Wall Portion Thermal Stress Management
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Solution Overview
Problem
The existing semiconductor memory devices with three-dimensional structures face stress issues from peripheral structures during manufacturing, leading to potential short circuits due to thermal stress, especially as the number of stacked layers increases, causing distortion and inclining of components like bit lines and source lines.
Innovation Solution
Incorporating a wall portion within the insulating portion surrounding the stacked body, which reduces the volume of insulating material directly surrounding the stacked body, thereby relaxing thermal stress and preventing distortion, and ensuring uniform distances between the wall portion and the memory cell array to distribute stress evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a large volume of insulating material surrounds the stacked body, then structural support is improved, but thermal stress increases causing distortion and potential short circuits
Solution Approach 1:
The insulating portion is segmented into multiple regions: a first insulating region directly surrounding the stacked body, a second insulating region surrounding the first region, and a wall portion extending between them. This segmentation allows the structure to maintain support while reducing continuous thermal stress accumulation.
Solution Approach 2:
Different regions of the insulating structure have different properties optimized for their specific functions. The first insulating region provides close support, the wall portion manages stress distribution, and the second insulating region provides outer containment. This local differentiation resolves the contradiction between support and stress reduction.
2Quantity of substance
If the number of stacked layers increases, then storage capacity is improved, but thermal stress and distortion increase
Solution Approach 1:
The solution moves from a simple radial insulation model to a multi-dimensional insulating structure with vertical wall portions and multiple insulating regions. This dimensional expansion allows stress management capabilities that scale with the number of stacked layers, enabling increased storage capacity without proportional increases in thermal stress.
3Object-affected harmful factors
If insulating material is reduced, then thermal stress is relaxed, but structural support may be compromised
Solution Approach 1:
The wall portion acts as an intermediary element between the inner and outer insulating regions. It mediates the transition from high-support-needed areas to low-stress areas, allowing the structure to maintain both support and stress relaxation simultaneously through this intermediate component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the likelihood of short circuits and maintains the structural integrity of the semiconductor device by minimizing thermal stress and maintaining the alignment of critical components like bit lines and source lines, regardless of the number of stacked layers.
Implementation Method 1
the stacked body may be affected by a stress from a peripheral structure
Data Source
AI summary
According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion is provided in the stacked body and extends in a staking direction of the stacked body. The insulating portion is provided around the stacked body and surrounds the stacked body. The wall portion is provided in the insulating portion and is separated from the stacked body. The wall portion extends in the stacking direction and in a first direction crossing the stacking direction.