Semiconductor Device Warpage Control via Silver Nickel Metal Layers
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Solution Overview
Problem
Semiconductor devices face issues with warpage due to thermal expansion mismatches between metal and semiconductor substrates, leading to mounting defects and high on-resistance, which existing technologies struggle to address simultaneously.
Innovation Solution
A chip-size-package-type semiconductor device with a silver metal layer and a nickel metal layer, where the silver layer has a thickness of at least 30 μm and less than 60 μm, and the nickel layer has a thickness of at least 10 μm and less than 35 μm, along with specific electrode layouts and dimensions to manage warpage and on-resistance effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal layer thickness is increased to reduce on-resistance, then the on-resistance decreases, but the warpage of the semiconductor device increases due to thermal expansion mismatch
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the metal layer within a specific range (at least 30 μm and less than 60 μm) to achieve optimal balance between electrical performance and mechanical stability. This quantitative parameter optimization resolves the contradiction by finding the threshold value that satisfies both low on-resistance and minimal warpage requirements
Solution Approach 2:
The patent employs composite material structure by combining multiple layers with different properties: a metal layer (silver, copper, or aluminum) for electrical conduction, a buffer layer for mechanical stress management, and a protective layer for environmental protection. This multi-layer composite approach allows each layer to address specific requirements, enabling low on-resistance while compensating for thermal expansion differences through the buffer layer
2Shape
If the metal layer thickness is increased to reduce warpage, then the warpage decreases, but the on-resistance increases
Solution Approach 1:
The patent resolves this contradiction by establishing an upper bound for metal layer thickness (less than 60 μm) to prevent excessive warpage compensation that would increase on-resistance. The specific threshold of 60 μm represents the optimal balance point where further thickening would yield diminishing warpage reduction benefits while continuously increasing electrical resistance
Solution Approach 2:
The patent introduces a buffer layer as an intermediary between the metal layer and the semiconductor substrate. This buffer layer mediates the mechanical stress and thermal expansion differences, allowing the metal layer to maintain optimal thickness for electrical performance while the buffer layer handles the warpage compensation function
3Shape
If a conductive layer is formed on the metal layer to reduce warpage, then the warpage decreases, but the manufacturing complexity increases and the layer becomes too thick
Solution Approach 1:
The patent resolves this contradiction by optimizing the thickness parameters of existing layers rather than adding new layers. By precisely controlling the metal layer thickness (30-60 μm) and introducing a buffer layer with controlled thickness, the patent achieves warpage reduction through parameter optimization of existing structural elements rather than adding complex multi-layer conductive structures
4Reliability
If the semiconductor device is mounted via flip-chip method with solder, then the electrical connection is achieved, but joint defects occur due to solder protrusion under high temperature
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the metal layer before the mounting process. This protective layer is prepared in advance to prevent solder protrusion and joint defects during the high-temperature reflow soldering process, addressing the mounting defects before they occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively inhibits warpage and reduces on-resistance while minimizing solder joint defects, ensuring reliable mounting and efficient electrical performance.
Implementation Method 1
the coefficient of thermal expansion of the metal layer is greater than the coefficient of thermal expansion of the semiconductor substrate, which causes the semiconductor device to warp from changes in temperature
Data Source
AI summary
A semiconductor device includes: a semiconductor (10 μm≤tsi≤30 μm); a metal layer (30 μm≤tag≤60 μm) comprising Ag; a metal layer (10 μm≤tni≤35 μm) comprising Ni; and transistors. The transistors include a source electrode and a gate electrode on the semiconductor layer. The metal layer functions as a common drain region for the transistors. The ratio of the lengths of the longer side and the shorter side of the semiconductor layer is at most 1.73. The ratio of the surface area and the perimeter length of each electrode included in the source electrode is at most 0.127. The cumulative surface area of the source electrode and the gate electrode is at most 2.61 mm2. The length of the shorter side of the source electrode is at most 0.3 mm, and 702<2.33×tsi+10.5×tag+8.90×tni<943 is satisfied.