Semiconductor Chip Wave-Shaped Passivation Layer Thermal Bump Reliability

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Solution Overview

Problem

Current semiconductor chips with TSV structures face challenges in achieving high performance, large capacity, miniaturization, and lightness, particularly due to issues with thermal bump formation and contact defects caused by uneven passivation layer surfaces and diffuse reflection during photolithography.

Innovation Solution

The semiconductor chip design features a passivation layer with a wave-shaped top surface and uniformly spaced uppermost wirings, ensuring consistent thermal bump formation and preventing diffuse reflection, thereby maintaining reliable contact between signal and thermal bumps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional planar passivation layer is used, then the manufacturing process is simple, but contact defects occur due to uneven surfaces and diffuse reflection during photolithography

Engineering Contradiction:

Improvecontact reliabilityVSAvoidpassivation layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The passivation layer top surface is designed with a wave shape instead of a planar surface. This curvature modifies the surface topology to prevent diffuse reflection during photolithography, ensuring uniform light exposure and accurate pattern formation for thermal bumps, thereby eliminating contact defects while maintaining manufacturing feasibility

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The invention changes the geometric parameter of the passivation layer surface from flat to wave-shaped. This parameter modification alters the optical properties during photolithography, preventing diffuse reflection and ensuring consistent thermal bump formation, thus improving contact reliability without significantly complicating the manufacturing process

Inventive Principle:

Principle #35Parameter changes

2Reliability

If uniformly spaced uppermost wirings are used, then diffuse reflection is prevented, but thermal bump formation consistency becomes challenging on uneven surfaces

Engineering Contradiction:

Improvethermal bump formation consistencyVSAvoidthermal bump placement accuracy

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The wave-shaped passivation layer surface is designed to work in conjunction with uniformly spaced uppermost wirings. The curvature compensates for surface unevenness, ensuring that photolithography exposure is uniform across the entire surface, which enables consistent thermal bump formation and precise placement even with simple wiring patterns

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The wave shape of the passivation layer is specifically designed in regions where thermal bumps are formed, while maintaining uniform wiring spacing in other regions. This localized optimization ensures that each area has the appropriate characteristics for its function: the wave shape prevents diffuse reflection for bump formation, while uniform wiring spacing maintains electrical connectivity

Inventive Principle:

Principle #3Local quality

3Quantity of substance

If multiple TSV structures are integrated for high capacity, then chip capacity increases, but thermal management becomes more difficult due to increased heat generation

Engineering Contradiction:

Improvechip capacityVSAvoidchip temperature

Core Design Contradiction:

Quantity of substanceVSTemperature

Solution Approach 1:

The invention converts the harmful effect of heat generation from multiple TSV structures into a beneficial thermal management solution. By integrating thermal bumps that contact the back surface of the substrate, the heat generated by high-capacity TSV structures is efficiently conducted away, transforming the thermal challenge into an opportunity for enhanced heat dissipation design

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

4Weight of moving object

If miniaturization is pursued for lightness, then chip weight and size decrease, but manufacturing precision requirements increase

Engineering Contradiction:

Improvechip weightVSAvoidfeature size control

Core Design Contradiction:

Weight of moving objectVSManufacturing precision

Solution Approach 1:

The wave-shaped passivation layer surface modifies the optical parameters during photolithography, preventing diffuse reflection that would otherwise cause pattern distortion. This enables precise feature formation even at miniaturized dimensions, allowing the chip to achieve lightness through size reduction while maintaining the manufacturing precision required for small features

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10134702B2Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip

Publication Date: 2018.11.20 SAMSUNG ELECTRONICS CO LTD

AI summary

The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.