Semiconductor Memory Wear-Leveling via Random Mapping Initialization

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Solution Overview

Problem

Existing wear-leveling techniques for semiconductor memory devices result in substantial overhead due to simultaneous performance on multiple memory cells or regions reaching access limits, leading to uneven deterioration and potential loss of data reliability.

Innovation Solution

A semiconductor system with a control device that initializes mapping information to random values using seed values from a volatile memory device, incorporating a linear feedback shift register (LFSR) to generate these values, and updates based on wear-leveling performance, while considering temperature for optimal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If wear-leveling techniques continuously update address mapping table to distribute access uniformly, then memory device life is prolonged, but overhead increases substantially when multiple memory cells or regions simultaneously reach access limit

Engineering Contradiction:
Improvememory device lifeVSAvoidoverhead
Core Design Contradiction:
Duration of action of stationary objectVSProductivity

Solution Approach 1:

The patent applies preliminary action by initializing mapping information to random values before the wear-leveling operation begins. This pre-initialization with random values ensures that when multiple memory cells or regions simultaneously reach the access limit, they do not all trigger wear-leveling operations at the same time, thereby reducing overhead while still achieving uniform access distribution throughout the memory device life.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If mapping information is initialized to same value for all memory cells, then wear-leveling operation is simplified, but write count numbers simultaneously reach preset limit causing overhead increase

Engineering Contradiction:
Improveinitialization simplicityVSAvoidoverhead
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies asymmetry by initializing mapping information to random values rather than identical values for all memory cells. This asymmetric initialization ensures that memory cells have different starting write count numbers, which prevents them from simultaneously reaching the preset access limit. The random values create a staggered wear pattern that reduces the overhead of wear-leveling operations while maintaining the simplicity of the initialization process.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces overhead and ensures more uniform access distribution, prolonging memory device life by minimizing wear on specific regions and maintaining data reliability.

Implementation Method 1

The control device may include a linear feedback shift register (LFSR) for generating the random values based on the seed values.

Methodology Applied
Scientific EffectLinear feedback shift register:

Data Source

PatentUS10936481B2Semiconductor system and method for operating the semiconductor system
Publication Date: 2021.03.02 SK HYNIX INC
  • US10936481B2 patent drawing
  • US10936481B2 patent drawing
  • US10936481B2 patent drawing

AI summary

A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.