Semiconductor Device Well Contact Layer Placement
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Solution Overview
Problem
The challenge in semiconductor memory devices, such as NAND-type flash memories, is the difficulty in manufacturing high-integration levels due to the need for scaling down individual components, which complicates the manufacturing process and can lead to issues like leak current and non-uniform MOSFET characteristics.
Innovation Solution
The semiconductor device design features alternately arranged p-type and n-type wells with high impurity concentration well contact layers and source/drain layers, arranged in a simple repetitive pattern, with well contact layers separated from element isolation insulators to prevent crystal faults and reduce leak current, while maintaining uniformity and facilitating lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scaling down individual components is performed to achieve high integration, then integration level is improved, but manufacturing difficulty increases and MOSFET characteristics become non-uniform
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations: high impurity concentration well contact layers at the ends of active areas and lower impurity concentration source/drain layers in the middle portions. This local differentiation maintains uniform MOSFET characteristics across the device while enabling high integration, as each region is optimized for its specific function without compromising overall device uniformity
Solution Approach 2:
The patent utilizes parameter changes by varying the impurity concentration parameter across different regions of the semiconductor device. The well contact layers have higher impurity concentrations than the source/drain layers, and both differ from the channel region impurity concentrations. This parameter variation allows the device to maintain uniform characteristics while achieving high integration levels
2Quantity of substance
If well contact layers are formed adjacent to element isolation insulators to reduce area, then integration is improved, but crystal faults occur and leak current increases
Solution Approach 1:
The patent extracts the well contact layers from their conventional positions adjacent to element isolation insulators and relocates them to the end parts of active areas. This extraction eliminates the harmful interaction between well contact layers and isolation insulators that causes crystal faults and leak current, while maintaining the electrical connection function of the well contact layers
Solution Approach 2:
The patent introduces the active area as an intermediary region between the well contact layers and the rest of the device structure. By positioning well contact layers within the active area rather than adjacent to isolation insulators, the active area serves as a mediator that prevents direct contact between the well contact layers and isolation structures, thereby eliminating crystal fault generation and leak current paths
Data Source
AI summary
A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side.