Semiconductor Well Layout for Gate Dielectric ESD Protection
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Solution Overview
Problem
Integrated circuits (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses, particularly during human-body model (HBM) tests, leading to potential failure due to voltage spikes that exceed the threshold of gate dielectrics, causing damage to semiconductor devices.
Innovation Solution
The IC design includes semiconductor devices disposed in separate well regions with distinct body contacts, allowing for voltage drops across multiple devices, thereby reducing the voltage spike at the gate electrode below the threshold for damage, enhancing ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor devices are placed in a shared well region with common body contact, then device complexity is reduced, but voltage spikes during ESD events exceed gate dielectric thresholds causing damage
Solution Approach 1:
The patent divides the previously shared well region into separate well regions for different semiconductor devices. Each well region has its own independent body contact, segmenting the ESD current path. This segmentation prevents voltage spikes from affecting multiple devices simultaneously, as each device's gate dielectric is protected by its own isolated body contact reference potential.
2Reliability
If separate well regions with distinct body contacts are used, then ESD protection is improved, but device complexity and layout area increase
Solution Approach 1:
The patent merges adjacent well regions that would otherwise be completely separate, allowing them to share certain fabrication processes and layout space while maintaining electrical isolation through strategic placement of isolation structures. The body contacts are positioned to serve multiple devices within the merged region, reducing overall complexity compared to fully independent well regions for each device.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.