Semiconductor Well Structure with Protruding Pickup Sections for LOD Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor designs face challenges in efficiently integrating pickup cells due to the Length of Oxide Definition (LOD) effect, which affects the performance of transistors near isolation edges, leading to reduced utilization of silicon wafer area and increased complexity.
Innovation Solution
The design incorporates N and P wells with protruding and recessed sections, allowing continuous fins for both types of pickup and regular cells, reducing the spacing between active regions and minimizing the impact of the LOD effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pickup cells are integrated with regular cells in standard layouts, then device functionality is achieved, but silicon area usage increases and manufacturing complexity increases due to the LOD effect
Solution Approach 1:
The patent applies asymmetry by designing pickup cells with non-traditional geometries including protruding sections that extend into adjacent cell regions and irregularly shaped active regions. This asymmetric layout allows pickup cells to share space with regular cells more efficiently, reducing overall silicon area usage while maintaining functionality and minimizing LOD effect impact on transistor performance
Solution Approach 2:
The patent implements nesting by placing pickup cells within or adjacent to regular cell regions, where protruding sections of pickup cells extend into spaces between regular cell structures. This nested arrangement allows both cell types to coexist in overlapping or interdigitated patterns, increasing integration density without proportionally increasing total area
2Area of stationary object
If pickup cells are made smaller to increase integration, then area usage improves, but manufacturing precision requirements increase due to reduced spacing between active regions
Solution Approach 1:
The patent utilizes dimensional optimization by carefully controlling the extent and positioning of protruding sections in the lateral plane, allowing pickup cells to occupy otherwise wasted space between regular cells. This dimensional approach reduces the effective footprint of pickup cells without compromising their electrical functionality or requiring excessive manufacturing precision
3Reliability
If continuous fins are used for both pickup and regular cells, then transistor performance improves by minimizing LOD effect, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by implementing a common fin formation process that serves both pickup cells and regular cells simultaneously. The same epitaxial growth and patterning steps create continuous fins that function for both cell types, eliminating the need for separate fin formation processes and reducing overall manufacturing complexity while ensuring consistent transistor performance
Data Source
AI summary
A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.