Semiconductor Well Layout Rearrangement for SEU Immunity
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Solution Overview
Problem
Existing methods for mitigating single event upsets (SEUs) in semiconductor circuits, such as the LEAP approach and guard rings, are ineffective against parasitic bipolar action and increase the circuit's footprint.
Innovation Solution
A computer processor determines and increases the distance metric between complementary well types in a semiconductor circuit layout by rearranging or reshaping wells, thereby enhancing SEU immunity without expanding the circuit's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard rings are formed between P wells and N wells to protect against parasitic bipolar action, then SEU immunity is improved, but die space is consumed
Solution Approach 1:
The patent extracts and removes the parasitic bipolar transistors from the substrate by forming isolation regions that completely separate P-type and N-type wells. This eliminates the harmful parasitic structures rather than adding protective elements around them, thus improving SEU immunity without consuming additional die space.
Solution Approach 2:
The patent introduces isolation regions as intermediary structures between P-type and N-type wells. These isolation regions act as mediators that completely separate the complementary wells, preventing parasitic bipolar action while maintaining compact layout. The isolation regions serve as the intermediate element that resolves the conflict between proximity (for area efficiency) and separation (for SEU immunity).
2Reliability
If further separation of nodes in the layout is provided to protect against parasitic bipolar action, then SEU immunity is improved, but die space is consumed
Solution Approach 1:
The patent extracts and removes the parasitic bipolar transistors from the substrate by forming isolation regions that completely separate P-type and N-type wells. This eliminates the harmful parasitic structures rather than adding protective elements around them, thus improving SEU immunity without consuming additional die space.
Solution Approach 2:
The patent changes the separation parameter between P-type and N-type wells by introducing isolation regions. Instead of uniformly increasing the distance between all nodes, the isolation regions selectively separate complementary wells at critical interfaces, optimizing the separation parameter where it matters most for preventing parasitic bipolar action while minimizing overall area impact.
Data Source
AI summary
According to a method of preparing a layout of semiconductor circuit elements, a computer processor determines a first value of a distance metric that describes a separation between at least one well of a first type and at least one well of a second type in a first layout of a circuit design represented in a memory coupled to the computer processor. The at least one well of the first type and the at least one well of the second type are rearranged into a second layout. The method determines a second value of the distance metric that describes separation between the at least one well of the first type and the at least one well of the second type in the second layout. The second layout is stored in response to the second value of the distance metric being greater than the first value of the distance metric.