Semiconductor Well Layout for Unified Low- and Middle-Voltage Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing semiconductor devices with complex structures and high voltage requirements, leading to increased costs and complexity, particularly in achieving the necessary electrical characteristics for low-voltage and middle-voltage devices within display driving devices.
Innovation Solution
The semiconductor device incorporates a low-voltage device and two middle-voltage devices with distinct well regions and impurity concentrations, allowing for the use of a single manufacturing process to achieve the required electrical characteristics, thereby reducing manufacturing costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate manufacturing processes are used for low-voltage and middle-voltage devices to achieve distinct electrical characteristics, then device characteristics are secured, but manufacturing complexity and costs increase
Solution Approach 1:
The patent combines the manufacturing processes for low-voltage and middle-voltage devices into a single unified process. Multiple well regions (low-voltage well region, first middle-voltage well region, second middle-voltage well region) are formed simultaneously using a single ion implantation process with different impurity concentrations, eliminating the need for separate manufacturing steps while maintaining distinct electrical characteristics for each device type.
Solution Approach 2:
The unified manufacturing process serves multiple functions by simultaneously creating different well regions with different electrical characteristics. The single ion implantation process accomplishes what previously required multiple separate processes, making the manufacturing system more efficient and reducing overall process complexity while maintaining the ability to produce both low-voltage and middle-voltage devices.
2Reliability
If multiple well regions with different impurity concentrations are formed using separate ion implantation processes, then distinct electrical characteristics are achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges multiple ion implantation processes into a single simultaneous ion implantation process. The low-voltage well region, first middle-voltage well region, and second middle-voltage well region are all formed in one manufacturing step by implanting impurities at different concentrations simultaneously, thereby reducing manufacturing costs while maintaining distinct electrical characteristics for each device type.
3Productivity
If geometric size is reduced to increase production efficiency, then productivity improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent addresses the increased device complexity resulting from geometric scaling by merging multiple well formation processes into a single simultaneous ion implantation process. This consolidation simplifies the manufacturing workflow and reduces process steps, thereby improving production efficiency and productivity despite the reduced geometric dimensions and increased device integration density.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a low-voltage device configured to receive a first level voltage and a first middle-voltage device configured to receive a second level voltage higher than the first level voltage. The low-voltage device includes a low-voltage well region, the first middle-voltage device includes a 1-1st middle-voltage well region and a 1-2nd middle-voltage well region, and the low-voltage well region and the 1-1st middle-voltage well region have a first well concentration with respect to a first conductivity type impurity.