Semiconductor Layout Freedom via Segmented Well Power Feeding
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Solution Overview
Problem
The miniaturization of semiconductor devices with memory units is hindered by the limited degree of freedom in layout design due to simple power feeding region arrangements, which restricts the downsizing of semiconductor devices, especially when using manufacturing processes with minimum processing sizes like 28 nm, where all gate layers need to be extended in the same direction for accuracy.
Innovation Solution
A semiconductor device design featuring a first well region with multiple parts and a power feeding region of higher impurity concentration, where the power feeding region is strategically positioned to supply voltage to adjacent well regions, allowing for a more efficient layout by eliminating bottlenecks and increasing the area of power feeding diffusion layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If all gate layers are extended in the same direction to ensure processing accuracy in minimum processing size manufacturing, then manufacturing precision is improved, but the degree of freedom of layout is reduced
Solution Approach 1:
The well region is divided into multiple parts (first well part, second well part, third well part) with different orientations. The first and second well parts have gate layers extending in a first direction, while the third well part has gate layers extending in a second direction different from the first direction. This segmentation allows different gate orientations in different regions, resolving the contradiction between maintaining processing accuracy and preserving layout flexibility.
2Device complexity
If simple power feeding region arrangement is used, then device complexity is reduced, but the degree of freedom of layout is reduced
Solution Approach 1:
Different well parts are assigned different functions and orientations based on local requirements. The first and second well parts are configured for specific transistor types with gate layers in the first direction, while the third well part is configured for different transistor types with gate layers in the second direction. This local differentiation maintains functional clarity while enabling layout flexibility.
3Adaptability or versatility
If well regions are arranged to accommodate multiple transistor types, then adaptability of the device is improved, but the area of the semiconductor device increases
Solution Approach 1:
Multiple well parts (first, second, and third well parts) are arranged in an integrated configuration where they share common power feeding regions and are closely positioned. This merging approach allows different transistor types to be accommodated in a compact area, reducing the overall semiconductor device area while maintaining adaptability.
Data Source
AI summary
A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.