Semiconductor Well Region Impurity Profile for Withstand Voltage
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Solution Overview
Problem
Semiconductor devices with existing well region structures experience electric field concentration at the outer side edge portion, leading to reduced withstand voltage due to uniform impurity concentration across the well region.
Innovation Solution
A semiconductor device structure where the second conductivity type impurity concentration of the outer side edge portion of the well region is lower than the inner side edge portion, achieved through a method involving oxidation treatment to form an oxide film that exposes the inner side edge and covers the outer side edge, thereby reducing electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform impurity concentration is used across the well region, then manufacturing process is simple, but electric field concentration occurs at the outer side edge portion reducing withstand voltage
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the well region. Specifically, the outer side edge portion has a lower second conductivity type impurity concentration compared to the inner side edge portion, which suppresses electric field concentration at the outer edge while maintaining adequate doping levels in the inner region for proper device operation.
Solution Approach 2:
The patent changes the impurity concentration parameter spatially within the well region. By reducing the second conductivity type impurity concentration at the outer side edge portion relative to the inner side edge portion, the electric field distribution is modified to prevent concentration effects that would reduce withstand voltage.
2Manufacturing precision
If oxidation treatment is performed to form oxide film covering outer side edge, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing oxidation treatment to form an oxide film on the outer side edge portion of the well region before final impurity introduction. This oxide film serves as a mask or protective layer that prevents impurity diffusion in the outer edge region, thereby creating the desired non-uniform impurity concentration profile. The selective oxidation approach enables precise control over where impurities are introduced into the semiconductor layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves improved withstand voltage by suppressing electric field concentration at the outer side edge portion, enhancing the structural integrity and performance.
Implementation Method 1
a step of performing an oxidation treatment to form an oxide film, which exposes an inner side edge portion positioned at the active region side in the well region, and covers an outer side edge portion positioned at an opposite side with respect to the active region in the well region
Data Source
AI summary
A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion.