Semiconductor Device Well Region Segmentation for Channel Resistance
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Solution Overview
Problem
Conventional semiconductor devices struggle to reduce channel resistance effectively due to the constant width of the well region, which limits the reduction of electric field concentration and resistance.
Innovation Solution
A semiconductor device design featuring a first conductivity-type drift region and second conductivity-type well regions, where the second well region has a shorter lateral width and extends deeper into the substrate, allowing for a larger channel width and reduced implantation energy, thereby decreasing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the well region is formed at a constant width, then the manufacturing process is simple, but the channel resistance cannot be reduced effectively
Solution Approach 1:
The well region is divided into two segments: a first well region extending from the surface to a first depth, and a second well region extending from the first depth to a second depth greater than the first depth. This segmentation allows each segment to have different widths optimized for specific functions, resolving the contradiction between manufacturing simplicity and channel resistance reduction.
Solution Approach 2:
Different portions of the well region are given different local qualities: the first well region has a first width optimized for surface-level operations, while the second well region has a second width optimized for deeper channel formation. This local differentiation enables reduced channel resistance in critical areas while maintaining overall structural integrity.
2Reliability
If the well region extends deeper into the substrate, then the channel width increases and channel resistance decreases, but the implantation energy required increases
Solution Approach 1:
The ion implantation process is segmented into two stages: first implantation to create the first well region at lower energy levels, and second implantation to create the second well region at greater depths. This segmentation allows optimization of implantation energy at each stage, reducing the total energy required compared to a single deep implantation process.
Solution Approach 2:
The first well region is formed as a preliminary structure before forming the second well region. This preliminary action creates a foundation that facilitates subsequent deeper implantation, allowing the second well region to be formed with optimized energy levels rather than requiring maximum energy from the start.
3Device complexity
If the second well region has the same width as the first well region, then the structure is simple, but the electric field concentration is not effectively reduced
Solution Approach 1:
The second well region is given a different local quality (width) compared to the first well region. Specifically, the second well region has a second width that differs from the first width, creating a tapered or varied width structure that effectively reduces electric field concentration at critical interfaces while maintaining manufacturing feasibility.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
A semiconductor device includes: a substrate (1); a first conductivity-type drift region (4) disposed on a principal surface of the substrate (1); a second conductivity-type first well region (21) extending from a second principal surface of the drift region (4) in a direction perpendicular to the second principal surface and having a bottom portion reaching inside of the substrate (1); a second conductivity-type second well region (22) being in contact with the bottom portion and disposed at a portion inside the substrate (1) located below the bottom portion; and a first conductivity-type source region (3) extending in a perpendicular direction from a region of the second principal surface provided with the first well region (21), and reaching the second well region (22). In a direction parallel to the second principal surface and oriented from a source electrode (15) to a drain electrode (16), a distance of the second well region (22) in contact with a gate insulating film (6) is shorter than a distance of the first well region (21) in contact with the gate insulating film (6).