Simultaneous Annealing of Semiconductor Window Layers

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Solution Overview

Problem

Thin film photovoltaic cells, such as CdTe/CdS hetero-junction-based cells, face challenges in light transmission and charge collection due to poor quality of the window layer, leading to reduced performance and increased manufacturing costs.

Innovation Solution

A method of simultaneously thermally processing two semiconductor assemblies with facing semiconductor layers, using techniques like sputtering and vacuum conditions, to enhance the quality and recrystallization of the window layer, thereby improving light transmission and junction performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the window layer is made thinner to improve light transmission, then light transmission increases, but charge collection performance deteriorates

Engineering Contradiction:
Improvelight transmissionVSAvoidcharge collection performance
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent changes the crystalline structure parameter of the window layer from amorphous or polycrystalline to single-crystalline orientation. This parameter change allows the window layer to maintain thin thickness for light transmission while the single-crystalline structure provides improved charge collection performance through better atomic arrangement and reduced defects at the heterojunction interface.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If traditional thermal processing is used for CdS films, then processing is simple, but sublimation occurs and quality deteriorates

Engineering Contradiction:
Improveprocessing simplicityVSAvoidfilm quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent employs an inert atmosphere (vacuum or inert gas environment) during thermal processing of the CdS window layer. This inert environment prevents sublimation of the CdS material by maintaining controlled pressure and atmosphere conditions, allowing high-temperature processing to achieve single-crystalline orientation without material loss or degradation, thus improving film quality while maintaining processing simplicity.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method results in higher efficiency photovoltaic cells with improved short circuit current, open circuit voltage, and fill factor by maintaining vapor pressure and reducing sublimation, facilitating higher-temperature processing of CdS films for better crystallinity and optical transmission.

Implementation Method 1

thermally processing a first semiconductor assembly comprising a first semiconductor layer disposed on a first support and thermally processing a second semiconductor assembly comprising a second semiconductor layer disposed on a second support

Methodology Applied
Scientific EffectThermal processing/Annealing: Annealing

Implementation Method 2

maintaining vapor pressure and reducing sublimation, facilitating higher-temperature processing of CdS films for better crystallinity and optical transmission

Methodology Applied
Scientific EffectVapor pressure: Vapour Pressure

Data Source

PatentEP2795684B1Methods for annealing semicondcutor window layers
Publication Date: 2018.02.14 FIRST SOLAR MALAYSIA
  • EP2795684B1 patent drawingFigure 1~5
  • EP2795684B1 patent drawingFigure 6~8
  • EP2795684B1 patent drawingFigure 9

AI summary

A method of manufacturing semiconductor assemblies is provided. The manufacturing method includes thermally processing a first semiconductor assembly comprising a first semiconductor layer disposed on a first support and thermally processing a second semiconductor assembly comprising a second semiconductor layer disposed on a second support. The first and second semiconductor assemblies are thermally processed simultaneously, and the first and second semiconductor assemblies are arranged such that the first semiconductor layer faces the second semiconductor layer during the thermal processing.