Semiconductor Package Substrate Opening for Wire Bond Clearance
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Solution Overview
Problem
The flip chip bonding process for semiconductor packages is not cost-effective compared to other bonding techniques, and it does not efficiently connect semiconductor dies to package substrates without risking damage to bonding wires during formation.
Innovation Solution
A semiconductor package design featuring a package substrate with an opening that has a wider width on one side than the other, allowing bonding wires to connect I/O pads on the semiconductor die to conductive pads on the substrate without physical contact with the opening's edges, thereby preventing damage and enabling a more cost-effective wire bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip bonding process is used to connect semiconductor die to package substrate, then connection reliability is improved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
Instead of using flip chip bonding where the die is inverted and bonded directly to the substrate, the patent inverts the approach by keeping the die in its normal orientation and routing wires through holes in the substrate. This allows the use of conventional wire bonding processes while achieving the same connection function, thereby reducing manufacturing cost and complexity.
Solution Approach 2:
The patent introduces bonding wires as an intermediary element that connects the I/O pads on the semiconductor die to conductive pads on the package substrate through holes. This mediator approach replaces the direct flip chip bonding interface with a wire-mediated connection, simplifying the manufacturing process while maintaining connection reliability.
2Ease of manufacture
If bonding wires are formed through openings in package substrate, then wire bonding cost effectiveness is improved, but risk of bonding wire damage from contact with opening edges increases
Solution Approach 1:
The patent employs asymmetric opening designs where the hole dimensions are deliberately made larger than the bonding wire diameter, creating a clearance gap. The opening width at the first side differs from the width at the second side, ensuring the bonding wire does not contact the edges during formation or operation, thus preventing wire damage while maintaining cost-effective wire bonding.
Solution Approach 2:
The patent designs the openings with predetermined larger dimensions before the bonding wire formation process, creating a protective clearance zone that cushions the bonding wire from potential damage. This pre-designed gap acts as a buffer that prevents contact between the wire and the opening edges, eliminating the risk of wire damage before it can occur.
3Device complexity
If opening width in package substrate is uniform, then manufacturing simplicity is improved, but bonding wires may contact substrate edges causing damage
Solution Approach 1:
The patent deliberately introduces asymmetry in the opening dimensions, where the width at the first side of the substrate differs from the width at the second side. This asymmetric design ensures adequate clearance between the bonding wire and substrate edges while maintaining reasonable manufacturing complexity through standardized hole formation processes.
Solution Approach 2:
The patent changes the dimensional parameters of the openings, specifically making the opening width larger than the bonding wire diameter and creating different widths at different sides of the substrate. This parameter adjustment provides the necessary clearance to prevent wire-edge contact while maintaining manufacturing feasibility through controlled hole formation processes.
Data Source
AI summary
The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor die, a package substrate and bonding wires. The semiconductor die has I/O pads arranged at an active side. The package substrate is provided with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and has an opening penetrating through the package substrate. The I/O pads are overlapped with the opening. A width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate. The bonding wires connect the I/O pads to the second side of the package substrate through the opening of the package substrate.