Semiconductor Wire-Bond Layout for Compact High-Current Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices is hindered by the difficulty in bonding a sufficient number of wires due to increased current density, which leads to heat generation and reliability issues, and existing solutions, such as stitch-bonding with a bus bar, require large insulating layers, making miniaturization challenging.
Innovation Solution
A semiconductor device configuration that includes an insulating substrate, a first semiconductor element, a conductive member with opposing portions, and wires connected to these elements in a specific layout, allowing for efficient wire bonding without increasing device size, thereby reducing insulation space and enabling miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stitch-bonding is used to bond twice the normal number of wires onto a semiconductor element, then the number of bonded wires is increased, but the insulating layer size must be enlarged to prevent bus bar displacement
Solution Approach 1:
The patent transitions from a planar insulating layer structure to a three-dimensional configuration where the insulating layer is recessed into the semiconductor element. By forming the insulating layer recess portion that extends into the semiconductor element depth direction, the patent achieves bus bar positioning stability without increasing the planar footprint of the insulating layer, thus resolving the contradiction between bonding more wires and maintaining insulating layer size.
Solution Approach 2:
The insulating layer is nested within the semiconductor element by forming a recess portion that extends into the semiconductor element. This nesting arrangement allows the bus bar to be positioned stably within the recessed insulating layer without requiring additional planar space, enabling increased wire bonding capacity while maintaining compact device dimensions.
2Reliability
If the insulating layer is spaced apart from the semiconductor element, then bus bar displacement is prevented, but the device size increases
Solution Approach 1:
Instead of spacing the insulating layer apart from the semiconductor element in the planar direction, the patent utilizes the depth dimension by forming a recess portion that extends into the semiconductor element. This vertical integration maintains bus bar positioning stability through the recessed structure while keeping the overall device footprint compact, resolving the contradiction between reliability and device size.
3Volume of moving object
If miniaturization of semiconductor elements is pursued, then surface area is reduced, but the number of wires that can be bonded decreases
Solution Approach 1:
The patent compensates for reduced surface area by utilizing the depth dimension through the insulating layer recess portion. This allows multiple wires to be bonded in a compact planar footprint while maintaining sufficient bonding capacity, as the recessed structure provides additional space for wire routing and bonding without increasing the semiconductor element's planar dimensions.
Solution Approach 2:
The insulating layer is segmented into a recessed portion that extends into the semiconductor element, creating distinct spatial zones for wire bonding. This segmentation allows efficient utilization of the limited surface area by organizing wire bonding paths in three-dimensional space, enabling adequate wire bonding capacity in miniaturized semiconductor elements.
Data Source
AI summary
A semiconductor device includes: an insulating substrate; a first semiconductor element connected to the insulating substrate; a conductive member disposed on the insulating substrate, and including a first opposing portion and a second opposing portion located opposite each other with respect to the first semiconductor element in plan view; a first wire connected to the first semiconductor element and the first opposing portion; and a second wire connected to the first semiconductor element and the second opposing portion, and located opposite the first wire with respect to a connection point where the first wire and the first semiconductor element are connected to each other in plan view.