Semiconductor Wire Bond Loop Layout for Narrow CSP Spacing
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Solution Overview
Problem
In semiconductor manufacturing, particularly for CSP devices, the narrow distance between the semiconductor chip and the wiring substrate leads to wire connection failures due to insufficient wire feeding and friction, causing shorts and instability in the wire loop during the bonding process.
Innovation Solution
The implementation of a reverse bonding system where a portion of each wire is disposed closer to the periphery than the wire connecting portion at the terminal, allowing for a longer wire length and stabilizing the loop shape by detouring the wire outside the connecting portion, thus matching the wire feed rate with the capillary movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If forward bonding system is used with narrow spacing, then wire bonding can be performed, but wire fails to enter between capillary and chip end causing connection failure
Solution Approach 1:
The patent inverts the bonding sequence by performing reverse bonding instead of forward bonding. The capillary first bonds to the chip electrode, then pulls the wire outward and bonds to the terminal on the wiring substrate. This inversion allows the wire to be properly fed and positioned, preventing the wire entry failure that occurs in forward bonding with narrow spacing.
2Object-affected harmful factors
If capillary is extended to prevent wire interference, then wire interference is prevented, but capillary bends at narrow portion disturbing ultrasonic wave conduction
Solution Approach 1:
By inverting the bonding sequence, the patent changes the spatial relationship between the capillary and wire during bonding. The wire is pulled outward from the chip side toward the terminal side, which prevents the wire from interfering with the capillary without requiring capillary extension that would cause bending and disrupt ultrasonic conduction.
3Reliability
If reverse bonding system is used, then wire connection failure is prevented, but wire length becomes insufficient for narrow spacing packages
Solution Approach 1:
The patent utilizes the lateral dimension by disposing a portion of the wire outside the connecting portion at the terminal. This allows the wire to have sufficient effective length for narrow spacing packages while maintaining proper bonding sequence and connection reliability.
4Ease of operation
If forward bonding is used with narrow spacing, then bonding can be performed, but friction between capillary and wire causes wear and connection failure
Solution Approach 1:
By reversing the bonding sequence, the patent changes the direction of wire feeding and capillary movement. The wire is pulled outward during bonding rather than being pushed through, which reduces friction between the capillary and wire, preventing wear and maintaining connection stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces shorting between the terminal and the chip, prevents wire connection failures, and allows for more stable wire bonding, even in small package sizes, by increasing the wire margin and maintaining a stable loop shape.
Implementation Method 1
moving a capillary to a direction distant from the semiconductor chip to pull the wire from the terminal
Implementation Method 2
pull the wire from the terminal
Data Source
AI summary
Wire connection failure in semiconductor device is prevented.A semiconductor device has a package substrate having, at the periphery of the main surface thereof, a plurality of bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the plurality of wires, and a plurality of solder bumps disposed on the back surface of the package substrate. The top of the loop of each of the wires is disposed outside the wire connecting portion so that the wire length wire can be increased in the connection between the bonding leads and the pads of the semiconductor chip. As a result, the wires have a stable loop shape and a wire connection failure can be prevented.