Semiconductor Package Wire Bonding to Reduce Bridge Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of silicon bridges in semiconductor packages leads to issues such as movement and incorrect attachment during manufacturing, resulting in decreased yield and warpage due to thermal expansion differences between silicon and organic substrate materials.
Innovation Solution
Electrical connection between semiconductor dies is achieved using bonding wires without silicon bridges, allowing signals to be exchanged between high-performance circuits through wires and low-performance circuits through the substrate, simplifying the manufacturing process and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon bridges are used to connect semiconductor chips to substrate, then electrical connection between fine-process chips and coarse substrate is achieved, but the silicon bridges may move or attach incorrectly during manufacturing, decreasing yield
Solution Approach 1:
The patent removes the silicon bridge component entirely from the system. Instead of using silicon bridges as intermediate connection elements, the invention directly connects semiconductor chips to the substrate through wire bonding, thereby eliminating the source of manufacturing defects associated with silicon bridge attachment and movement.
Solution Approach 2:
The patent introduces wire bonding as a new intermediary mechanism to replace silicon bridges for electrical connection. The wire bonding process uses bonded wires to establish electrical pathways between chip pads and substrate pads, serving the same functional purpose without the manufacturing issues of silicon bridges.
2Reliability
If silicon bridges are embedded in substrate, then electrical connection is achieved, but warpage occurs due to CTE difference between silicon and organic substrate materials
Solution Approach 1:
The patent extracts the silicon bridge element that causes thermal expansion mismatch. By removing silicon bridges from the package structure and using wire bonding instead, the source of CTE-induced warpage is eliminated, improving package flatness and stability.
3Quantity of substance
If integration density of passive or active devices increases, then more silicon bridges are required, but the structure becomes more complicated to correct overlay errors
Solution Approach 1:
The patent removes silicon bridges from the interconnection architecture entirely. This elimination simplifies the manufacturing process by removing the need for precise overlay alignment and complex embedding procedures, allowing higher integration density without proportional increases in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield of semiconductor packages by eliminating the problems associated with silicon bridge movement and attachment errors, while also simplifying the manufacturing process and reducing thermal warpage.
Implementation Method 1
a plurality of bonding wires electrically connecting the first semiconductor die and the second semiconductor die on the first semiconductor die and the second semiconductor die
Implementation Method 2
signals between low performance circuits in the first semiconductor die and the second semiconductor die are exchanged through the substrate
Implementation Method 3
a first redistribution layer structure... a second redistribution layer structure
Data Source
AI summary
A semiconductor package includes: a substrate; a first semiconductor structure on the substrate, wherein the first semiconductor structure includes a first redistribution layer structure and a first semiconductor die that is disposed on the first redistribution layer structure and includes a plurality of first through-semiconductor vias; a second semiconductor structure disposed side by side with the first semiconductor structure on the substrate, wherein the second semiconductor structure includes a second redistribution layer structure and a second semiconductor die that is disposed on the second redistribution layer structure and includes a plurality of second through-semiconductor vias; a plurality of bonding wires electrically connecting the first semiconductor die and the second semiconductor die on the first semiconductor die and the second semiconductor die; and a molding material surrounding the plurality of bonding wires and through which the plurality of bonding wires pass.