Semiconductor Package Wire Reinforcement for Fine-Pitch Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving increased reliability due to limitations in connecting substrates and maintaining structural integrity, particularly in package-on-package structures, which affect thermal radiation and durability.
Innovation Solution
The solution involves a semiconductor package design with a first and second substrate connected by wires, where under-fill patterns and a mold structure are used to reinforce the connection, enhancing the structural integrity and thermal radiation properties by preventing wire misalignment and short-circuits, and allowing for fine pitch arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are used to connect substrates in a package-on-package structure, then substrate connection is achieved, but wire misalignment and short-circuits may occur reducing reliability
Solution Approach 1:
The patent introduces under-fill patterns as intermediary structures between the wires and the mold structure. These under-fill patterns serve as positioning references that guide wire placement and prevent misalignment. The under-fill patterns act as a mediator that ensures precise wire positioning while maintaining connection reliability, directly resolving the contradiction between connection reliability and wire alignment precision.
2Productivity
If wires are arranged with fine pitch to increase connectivity, then substrate connection density improves, but wire structural integrity and alignment become more difficult to maintain
Solution Approach 1:
The patent applies under-fill patterns to wire surfaces before the wire bonding process. This preliminary action of coating wires with under-fill material provides structural reinforcement and stability beforehand, enabling the wires to maintain their integrity during fine pitch arrangement and subsequent processing. This resolves the contradiction by preparing wires in advance to handle the demands of high-density connectivity while maintaining structural stability.
Solution Approach 2:
The patent creates a composite structure by combining wire material with under-fill pattern material. This composite construction enhances the mechanical properties of the wires, providing both the electrical connectivity needed for fine pitch arrangements and the structural stability required to maintain alignment. The composite material approach directly addresses the contradiction between connection density and wire structure stability.
3Strength
If mold structure is formed to protect the semiconductor chip, then chip protection is achieved, but wire positioning accuracy may be compromised
Solution Approach 1:
The patent forms under-fill patterns on wire surfaces before the mold structure is applied. This preliminary action creates permanent positioning references that remain visible and functional even after the mold structure is in place. The under-fill patterns serve as ongoing guides for wire positioning, resolving the contradiction between chip protection and wire positioning accuracy by establishing positioning features in advance that survive the molding process.
4Reliability
If under-fill patterns are applied to wire surfaces, then wire stiffness and alignment are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the under-fill pattern formation process with existing wire preparation and bonding processes. By integrating the under-fill application into the established manufacturing workflow rather than adding it as a completely separate process, the patent improves wire alignment reliability while minimizing the increase in manufacturing process complexity. The merging approach resolves the contradiction by incorporating the beneficial under-fill technology into the existing process framework.
Data Source
AI summary
A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate, a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.