Vertically Stacked Semiconductor Wire Structure for GAA Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing complex three-dimensional transistor structures, such as those with nanowires, due to increased complexity and inefficiencies in processing and manufacturing as ICs scale down, requiring advancements in IC processing and manufacturing techniques.
Innovation Solution
The formation of a semiconductor device structure with gate all around (GAA) transistor structures, involving the use of vertically stacked semiconductor layers, recess formation, isolation features, dummy gate stacks, spacer elements, and metal gate stacks to enhance device performance and efficiency, particularly by optimizing the thickness and material composition of semiconductor wires and gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistor structures with nanowires are introduced to replace planar transistors, then functional density is improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor structure is divided into multiple discrete layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) that are formed separately and then combined. Each layer can be independently processed and optimized, reducing the overall manufacturing complexity while achieving the desired three-dimensional nanowire transistor structure with improved functional density
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically-stacked nanowire transistors by adding the vertical dimension. Multiple semiconductor layers are stacked vertically to form nanowire channels that extend in the vertical direction, enabling increased functional density while using standard planar fabrication processes for each layer
2Productivity
If semiconductor layers are scaled down to increase functional density, then production efficiency is improved, but processing complexity increases
Solution Approach 1:
Isolation features are formed between the semiconductor layers before the layers are fully processed and integrated. This preliminary formation of isolation structures allows subsequent processing steps to be performed independently on each semiconductor layer, simplifying the overall processing complexity while enabling efficient scaling to increased functional density
Solution Approach 2:
Different regions of the semiconductor structure are given different properties: semiconductor layers in active regions are optimized for carrier transport, while isolation features in between are optimized for electrical isolation. This local differentiation allows each region to be processed and optimized independently, reducing processing complexity while achieving high functional density through vertical stacking
Data Source
AI summary
Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.