Semiconductor Conducting Wire Layout for Short Circuit Prevention

Solution Overview

Problem

In semiconductor memory technologies, particularly in NAND-type flash memories and DRAMs, there is a challenge in preventing short circuits and misalignment of conducting wires with a line-and-space pattern, which affects chip size and reliability.

Innovation Solution

A layout design where conducting wires in the lead area have a smaller width than on the memory cell array, with a single-edged shape at one end, allowing for increased distance between wires and reducing the risk of short circuits and misalignment, thereby enabling a smaller chip size and higher storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conducting wires are formed with minimum processing dimensions in the memory cell array, then storage capacity is improved, but the risk of short circuit and misalignment increases in the lead area

Engineering Contradiction:

Improvestorage capacityVSAvoidshort circuit prevention

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The conducting wire width is varied by location: minimum width is used in the memory cell array to maximize storage capacity, while increased width is used in the lead area to prevent short circuits and misalignment. This local differentiation allows each region to have optimal wire dimensions for its specific function.

Inventive Principle:

Principle #3Local quality

2Reliability

If conducting wire width is increased in the lead area, then reliability is improved, but chip size increases

Engineering Contradiction:

Improveshort circuit preventionVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The conducting wire width is varied by location: minimum width is used in the memory cell array to maximize storage capacity, while increased width is used in the lead area to prevent short circuits and misalignment. This local differentiation allows each region to have optimal wire dimensions for its specific function.

Inventive Principle:

Principle #3Local quality

3Reliability

If conducting wire width is increased in the lead area, then misalignment resistance is improved, but chip size increases

Engineering Contradiction:

Improvemisalignment preventionVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The conducting wire width is varied by location: minimum width is used in the memory cell array to maximize storage capacity, while increased width is used in the lead area to prevent short circuits and misalignment. This local differentiation allows each region to have optimal wire dimensions for its specific function.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7915647B2Semiconductor integrated circuit

Publication Date: 2011.03.29 KIOXIA CORP

AI summary

A nonvolatile semiconductor memory concerning an example of the present invention comprises a cell array, a plurality of conducting wires extending from the cell array to a lead area, and a plurality of contact holes to arranged in the lead area so that a distance from the end of the cell array sequentially increases from one to the other of the plurality of conducting wires, each of the plurality of conducting wires having a first conducting wire portion having a first conducting wire width, a second conducting wire portion connected to the contact hole and having a second conducting wire width smaller than the first conducting wire width, and a third conducting wire portion electrically connecting the first conducting wire portion to the second conducting wire portion.