Semiconductor Package Wire Layout to Prevent Bonding Wire Shorts

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increasing demand for high-functionality and miniaturization in semiconductor packaging leads to longer bonding wires, which can cause loops to incline and potentially short circuit with neighboring wires, especially when using forward bonding methods.

Innovation Solution

The implementation of alternately arranged upper bonding wires with specific angles and positions to prevent contact between the capillary and adjacent bonding wires during the bonding process, using a reverse bonding method for certain wires to manage height differences and reduce loop inclination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bonding wires are made longer to accommodate miniaturization and high-functionality requirements, then the semiconductor package can achieve higher functionality and miniaturization, but the bonding wire loops may incline and contact neighboring bonding wires causing short circuits

Engineering Contradiction:
Improvehigh-functionalityVSAvoidshort circuit risk
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies asymmetry by alternating the arrangement of bonding wires at different angles (45° and 75°) relative to the semiconductor chip. This asymmetric angular arrangement creates varied loop trajectories that prevent uniform inclination and contact between adjacent bonding wires, thereby maintaining reliability while accommodating miniaturization requirements

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent introduces angular variation as an additional dimension to bonding wire arrangement. By controlling bonding wires to form different angles (45° and 75°) with the chip surface, the patent transforms a two-dimensional planar arrangement into a three-dimensional spatial configuration, enabling longer wires to clear neighboring wires and prevent short circuits

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If bonding wires are arranged in a conventional manner, then the manufacturing process is simple, but the bonding wire loops may incline and come into contact with adjacent bonding wires

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidbonding wire contact prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the angular parameter of bonding wire arrangement from a conventional uniform angle to alternating angles (45° and 75°). This parameter modification creates non-uniform loop trajectories that prevent inclination and contact between adjacent wires, achieving reliability improvement while maintaining manufacturing feasibility through systematic angular variation

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the bonding wire loop trajectory is reduced, then the risk of contact with capillary is reduced, but the bonding wire length must be precisely controlled

Engineering Contradiction:
Improvecapillary contact preventionVSAvoidloop trajectory control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses asymmetric angular arrangement (45° and 75° alternation) to create varied loop trajectories that naturally reduce the maximum loop height. This asymmetric configuration ensures that no single loop reaches excessive height that could contact the capillary, while the systematic nature of the angular variation maintains manufacturing precision requirements

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12456711B2Semiconductor package
Publication Date: 2025.10.28 SAMSUNG ELECTRONICS CO LTD
  • US12456711B2 patent drawing
  • US12456711B2 patent drawing
  • US12456711B2 patent drawing

AI summary

A semiconductor package includes a package substrate having substrate pads disposed in a first direction on one surface, a semiconductor chip having chip pads disposed in the first direction, and bonding wires connecting the chip pads and the substrate pads. The bonding wires include first and second bonding wires alternately connected to the substrate pads respectively, in the first direction, the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip, the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip and a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip.