Semiconductor Module Wire Routing to Prevent Resin Crack Breakage
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Solution Overview
Problem
Semiconductor modules face issues with bonding wire breakage due to thermal stress-induced cracks in the sealing resin, which concentrate near the edge of the plate-shaped connecting member, potentially damaging the wiring that crosses above it.
Innovation Solution
The semiconductor module design includes a substrate with electrically isolated circuit boards, a semiconductor element, a connecting member that bridges the upper surface electrode to a second circuit board, and bonding wires that cross the semiconductor element at a vertical position lower than the upper surface of the connecting member, ensuring the wires are not broken by cracks in the sealing resin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a bonding wire is wired above the plate-shaped connecting member to utilize dead space for miniaturization, then the semiconductor module size is reduced, but the bonding wire becomes vulnerable to breakage when cracks occur in the sealing resin
Solution Approach 1:
The patent relocates the bonding wire from a horizontal path above the connecting member to a vertical path through the connecting member. This dimensional change allows the wire to bypass the crack-prone sealing resin region while maintaining effective use of available space, thus preserving both miniaturization benefits and wire integrity
Solution Approach 2:
The plate-shaped connecting member serves as an intermediary structure that the bonding wire passes through. This intermediary approach allows the wire to traverse from one side to the other without暴露 to the sealing resin cracks that would occur if the wire ran above the connecting member, thus protecting the wire while maintaining compact layout
2Productivity
If the semiconductor module is miniaturized by effectively utilizing dead space, then productivity and compactness are improved, but thermal stress concentration in the sealing resin increases due to closer proximity of components
Solution Approach 1:
By routing the bonding wire vertically through the connecting member rather than horizontally above it, the patent reduces the horizontal dead space requirement. This allows for more compact horizontal arrangement of other components while the vertical wire path avoids the thermally stressed sealing resin region, thus improving miniaturization without exacerbating thermal stress concentration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents bonding wire breakage even when cracks occur in the sealing resin, enhancing the reliability and durability of the semiconductor module.
Implementation Method 1
when the semiconductor element operates and generates heat, thermal stress is applied to the sealing resin. Since the difference in thermal expansion coefficient and elastic modulus between the plate-shaped connecting member and the sealing resin is large, this thermal stress is concentrated on the sealing resin near the edge portion
Data Source
AI summary
A semiconductor module includes a substrate on which first, second, and third circuit boards that are electrically isolated from each other are formed; a semiconductor element arranged on the first circuit board; a connecting member that bridges an upper surface electrode of the semiconductor element and the second circuit board so as to electrically connect the upper surface electrode to the second circuit board; a wire that electrically connects the third circuit board to a first electrode that is located outside of where the first, second and third circuit boards are located in a plan view; and a sealing resin that covers and seals the substrate, the semiconductor element, the connecting member, and the wire, wherein the wire is wired from the third circuit board to the first electrode so as to cross the semiconductor element at a vertical position lower than an upper surface of the connecting member.