Semiconductor Wire Stack Joining for Reliable Copper Interconnects

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Solution Overview

Problem

The existing semiconductor apparatus manufacturing process, as described in PTL 1, requires a different joining method for copper foil and copper wire, leading to low productivity and reliability issues.

Innovation Solution

The semiconductor apparatus includes a semiconductor device with a metal layer, a lower wire member, and an upper wire member, where the lower wire member is temporarily joined to the metal layer, and the upper wire member is stacked and permanently joined with the lower wire member interposed, using the same joining method for both wire members.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper foil is joined to the electrode using silver-based sintering paste, then the joining is achieved, but the manufacturing process becomes complex and productivity decreases

Engineering Contradiction:
Improvejoining reliabilityVSAvoidmanufacturing productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies homogeneity by using the same copper material for both the foil and wire, and the same joining method (ultrasonic welding) for both components. This eliminates the need for different joining processes, simplifying manufacturing and improving productivity while maintaining reliable connections.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The patent makes the joining method universal by using ultrasonic welding for both copper foil and copper wire connections to the electrode. This single versatile process replaces the need for silver-based sintering paste, reducing manufacturing complexity and enhancing productivity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If copper foil is used between the electrode and copper wire, then electrical connection is achieved, but the device complexity increases due to multiple joining steps

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the copper foil from the structure, replacing it with a direct copper wire connection to the electrode. This simplifies the device structure and manufacturing process while maintaining reliable electrical connection, removing the intermediate component that added complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the function of the copper foil and copper wire into a single copper wire that directly connects to the electrode. This consolidation reduces the number of components and joining steps, simplifying the device structure and manufacturing process.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the productivity and reliability of the semiconductor apparatus by allowing the same joining method to be used for both wire members, preventing damage to the semiconductor device during the joining process, and reducing the risk of short circuits.

Implementation Method 1

performing ultrasonic vibration to the upper wire member with the lower wire member interposed therebetween using an ultrasonic welding device

Methodology Applied
Scientific EffectUltrasonic vibration: Ultrasonic Vibration

Data Source

PatentUS20250192098A1Semiconductor apparatus and method for manufacturing the same, and power conversion apparatus
Publication Date: 2025.06.12 MITSUBISHI ELECTRIC CORP
  • US20250192098A1 patent drawing
  • US20250192098A1 patent drawing
  • US20250192098A1 patent drawing

AI summary

A semiconductor apparatus includes a semiconductor device, a lower wire member, and an upper wire member. The semiconductor device includes a semiconductor device body having a main surface, and a metal layer. The lower wire member includes an end surface and an end surface. In a plan view of the main surface, the end surface and the end surface are located inside a periphery of the semiconductor device. The upper wire member is stacked on the lower wire member. In the plan view of the main surface, a portion of the upper wire member is located outside the periphery of the semiconductor device. The upper wire member is joined to the metal layer with the lower wire member being interposed therebetween.