Semiconductor Wiring Air Gap Structure for Misalignment Prevention
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Solution Overview
Problem
Existing semiconductor devices with air gaps in multilayer wiring layers face challenges in reducing inter-wiring capacitance and preventing short-circuiting due to via misalignment.
Innovation Solution
A semiconductor device structure featuring a first interlayer insulating layer with air gaps between wirings, where the upper ends of the interlayer insulating layer contact the side faces of the wirings, and a second interlayer insulating layer with a bottom face exposed to the air gap, maintaining a b/a ratio of less than 0.5, preventing misaligned via short-circuiting and effectively decreasing inter-wiring capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an air gap is made in the interlayer insulating layer to decrease inter-wiring capacitance, then inter-wiring capacitance is reduced, but misalignment of via over wiring causes short-circuiting
Solution Approach 1:
The patent introduces a vertical dimension solution by forming the bottom face of the second interlayer insulating layer below the upper faces of the wirings, creating a three-dimensional configuration that separates the via contact path from the air gap region, thus preventing short-circuits while preserving capacitance reduction
Solution Approach 2:
The first interlayer insulating layer acts as an intermediary structure that fills the space between the wirings and extends vertically to contact the side faces of the wirings, serving as a protective barrier that prevents direct contact between misaligned vias and the air gap while allowing the air gap to maintain its capacitance-reducing function
2Reliability
If the upper ends of the first interlayer insulating layer are positioned below the upper faces of the wirings, then via misalignment is tolerated, but manufacturing precision requirements increase
Solution Approach 1:
The first interlayer insulating layer is formed in advance with its upper ends contacting the side faces of the wirings, creating a pre-positioned protective structure that automatically prevents short-circuits even when vias are misaligned, thereby reducing the precision requirements for subsequent via formation steps
Solution Approach 2:
The patent employs an asymmetric configuration where the first interlayer insulating layer extends vertically to contact the wiring side faces, while the bottom face of the second interlayer insulating layer is positioned asymmetrically below the wiring upper faces, creating a non-uniform structure that provides alignment tolerance
Data Source
AI summary
A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a≦0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.