Semiconductor Wiring Layout for Stable Analog Power Potentials
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Solution Overview
Problem
The increasing functionality and terminal density in semiconductor devices lead to longer power supply paths with high inductance, causing fluctuations in power supply potential and reference potential due to noise interference, particularly affecting analog circuits.
Innovation Solution
The implementation of power supply and reference potential patterns in adjacent wiring layers, overlapping and extending in the same direction, with inductive coupling and electromagnetic shielding to reduce noise influence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of external terminals is increased to achieve higher functionality, then the functionality is improved, but the path distance for power supply increases leading to higher inductance and noise susceptibility
Solution Approach 1:
The patent transitions from planar routing to three-dimensional stacked routing by placing power supply and reference potential patterns in different wiring layers (first wiring layer and second wiring layer). This vertical arrangement in the layer dimension reduces the path distance and inductance while maintaining the required terminal density for high functionality.
Solution Approach 2:
The power supply pattern and reference potential pattern are arranged to overlap with each other in the vertical direction across different wiring layers. This nested arrangement allows the patterns to share the same horizontal footprint while maintaining electrical separation, effectively reducing the path distance without increasing the device footprint.
2Area of stationary object
If external terminals are arranged densely to downsize the device, then the device size is reduced, but the path distance for power supply increases leading to potential fluctuations
Solution Approach 1:
By utilizing the vertical dimension through multiple wiring layers, the patent achieves short power supply paths without increasing the horizontal device footprint. The stacked arrangement allows dense terminal packaging while maintaining short inductive paths for power delivery.
Solution Approach 2:
The reference potential pattern acts as an electromagnetic shield between the power supply pattern and external noise sources. This intermediary structure mitigates noise coupling and stabilizes the power supply potential despite the compact layout required for downsizing.
3Object-affected harmful factors
If the path distance for power supply is shortened to reduce inductance, then noise resistance is improved, but the layout complexity increases due to overlapping patterns in adjacent layers
Solution Approach 1:
The patent resolves layout complexity by moving the overlapping patterns to different wiring layers, utilizing the vertical dimension to achieve both short paths and noise immunity without complex in-plane routing. The layered structure simplifies the horizontal layout while achieving the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This layout reduces path inductance and noise interference, stabilizing the operation of analog circuits and improving semiconductor device performance.
Implementation Method 1
The first power supply potential pattern and the first reference potential pattern extend in the same direction while mutually overlapping
Implementation Method 2
One of the first power supply potential pattern and the first reference potential pattern is provided in a first wiring layer which is the nearest to a lower surface of the wiring substrate among the wiring layers. Another of the first power supply potential pattern and the first reference potential pattern is provided in a second wiring layer which is the next nearest to the lower surface after the first wiring layer
Data Source
AI summary
A semiconductor device includes a wiring substrate including a plurality of wiring layers, and a semiconductor chip including a first analog circuit. A power supply potential pattern capable of supplying a first power supply potential to the first analog circuit and a reference potential pattern capable of supplying a first reference potential to the first analog circuit are electrically connected with the first analog circuit. The power supply potential pattern is provided in a first wiring layer which is the nearest to a lower surface of the wiring substrate among the plurality of wiring layers. The reference potential pattern is provided in a second wiring layer which is the next nearest to the lower surface after the first wiring layer. The power supply potential pattern and the reference potential pattern extend in the same direction as each other while mutually overlapping with each other in transparent plan view.