Semiconductor Wiring Insulation via Intermediary Buffer Trace
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Solution Overview
Problem
In semiconductor integrated circuit devices, the potential difference between adjacent wiring traces for substrate bias control can exceed set values, making it difficult to ensure reliable insulation, especially in densely packed circuits, leading to increased chip size or labor-intensive design revisions.
Innovation Solution
The routing of wiring traces is optimized by interposing a first wiring trace with a prescribed voltage between second and third traces with higher or lower voltages, allowing automatic routing tools to maintain sufficient insulation without human intervention and reducing design labor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If minimum wiring spacing is reduced to increase integration density, then device functionality and versatility improve, but insulation reliability between wiring traces deteriorates
Solution Approach 1:
The patent introduces a buffer wiring trace with intermediate potential between high-potential and low-potential wiring traces. This intermediary trace acts as a mediator that reduces the potential gradient between adjacent traces with large potential differences, enabling smaller wiring spacing while maintaining insulation reliability in high-density integrated circuits
2Reliability
If wiring spacing is increased to ensure insulation between traces with high potential difference, then insulation reliability improves, but chip size increases
Solution Approach 1:
By inserting a buffer trace with intermediate potential between traces having large potential differences, the patent enables smaller spacing between critical wiring pairs. This intermediary approach maintains insulation reliability without requiring uniform increases in all wiring spacing, thus preventing chip size expansion
3Reliability
If manual routing adjustments are made to ensure insulation between traces, then insulation reliability improves, but design labor increases
Solution Approach 1:
The patent implements automatic identification and routing of buffer wiring traces by the routing tool itself. The system automatically determines which wiring traces require buffer insertion based on potential difference analysis and autonomously routes the buffer traces, eliminating the need for manual intervention while ensuring insulation reliability
Data Source
AI summary
Wiring is routed to assure insulation between wiring traces in a semiconductor integrated circuit device. The device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage that exceeds the prescribed voltage; and a third wiring trace that only takes on a voltage less than the prescribed voltage. Alternatively, the device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage less than the prescribed voltage; and a third wiring trace that takes on a voltage equal to or greater than the prescribed voltage. The wiring traces are routed at a certain wiring space in such a manner that the first wiring trace is interposed between the second and third wiring traces. The first wiring trace for which the potential difference is known to be small beforehand is routed so as to always be adjacent to the second wiring trace. Accordingly, the third wiring trace for which there is the possibility that the potential difference relative to the second wiring trace will become large is never placed directly adjacent the second wiring trace. As a result of such routing, wiring is implemented in such a manner that the insulation between traces can be sufficiently assured.