Semiconductor Wiring Structure With Dummy Pillars for CMP Flatness

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Chemical Mechanical Polishing (CMP) processes result in uneven top surfaces of conductive structures due to differing removal rates of metal and dielectric materials, leading to erosion and curvature issues in semiconductor devices.

Innovation Solution

Incorporation of dummy pillars made of dielectric material within the conductive structure to reduce pattern density, ensuring the conductive structure remains flatter after CMP processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If CMP process is used to planarize the surface, then surface flatness is improved, but top surface erosion of conductive structure occurs due to uneven removal rates

Engineering Contradiction:
Improvesurface flatnessVSAvoidtop surface erosion
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent introduces dummy pillars (local dielectric structures) within the conductive structure to create non-uniform pattern density distribution. This local modification causes the CMP process to remove dielectric material at different rates in different regions, compensating for the erosion that would otherwise occur on the conductive structure surface. The dummy pillars are strategically placed to achieve the desired pattern density adjustment in specific areas.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dummy pillars are formed in advance before the CMP process to pre-compensate for the erosion that will occur during CMP. By adjusting the pattern density through dummy pillars beforehand, the patent creates a counterbalancing effect that prevents the harmful erosion of the conductive structure surface during the subsequent CMP process.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If pattern density is increased to improve conductivity, then electrical performance is improved, but CMP erosion is worsened due to higher metal content

Engineering Contradiction:
Improveelectrical performanceVSAvoidCMP erosion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by introducing dummy pillars at specific locations within the conductive structure rather than uniformly increasing pattern density everywhere. This allows electrical performance to be maintained in functional areas while creating localized regions with adjusted pattern density that compensate for CMP erosion. The dummy pillars are placed strategically to achieve the right balance between electrical performance and erosion prevention.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces top surface erosion by up to 90-95% and maintains surface flatness, improving the quality and yield of semiconductor devices.

Implementation Method 1

The mechanical abrasion and chemical reactions work together to remove unwanted material

Methodology Applied
Scientific EffectMechanical abrasion: Abrasion

Implementation Method 2

Chemical Mechanical Polishing (CMP) combines aspects of both mechanical grinding and chemical etching

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS20250233068A1Semiconductor device, wiring structure and manufacturing method thereof
Publication Date: 2025.07.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250233068A1 patent drawing
  • US20250233068A1 patent drawing
  • US20250233068A1 patent drawing

AI summary

A wiring structure includes a first dielectric structure, a metal feature, a second dielectric structure and a metal pattern. The metal feature is embedded in the first dielectric structure. The second dielectric structure is disposed above the first dielectric structure and including dummy pillars and a main portion. The metal pattern is disposed above the first dielectric and including a conductive structure electrically connected with the metal feature. The dummy pillars are embedded in the conductive structure, and the main portion is surrounding the conductive structure.