Semiconductor Wiring Layout for CMP Planarization Without Voids
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Solution Overview
Problem
The challenge of securing planarization during chemical mechanical polishing (CMP) is exacerbated by high aspect ratios in wiring patterns, leading to difficulties in appropriate embedding and potential issues like dishing and void formation.
Innovation Solution
The implementation of wires with varying widths and intervals, combined with strategically formed recesses in the insulator layer, allows for controlled CMP by adjusting the width of mask materials during processing, facilitating embedding and reducing voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If embedding is performed in a pattern with higher aspect ratio to secure planarization of CMP, then planarization is improved, but embedding difficulty increases
Solution Approach 1:
The patent applies local quality by forming recesses selectively in specific regions where high aspect ratio patterns exist, rather than uniformly across the entire substrate. This allows the CMP process to achieve planarization in critical areas while maintaining easier embedding conditions in other regions, thus resolving the contradiction between planarization quality and embedding ease.
Solution Approach 2:
The patent segments the embedding process by dividing the pattern into regions with recesses and regions without recesses. This segmentation allows different embedding approaches to be applied to different regions, enabling planarization in high aspect ratio areas while avoiding excessive embedding difficulty in other areas.
2Manufacturing precision
If higher aspect ratio patterns are used for planarization, then CMP planarization is improved, but dishing and void formation increase
Solution Approach 1:
The patent applies local quality by forming recesses selectively in specific regions where high aspect ratio patterns exist, rather than uniformly across the entire substrate. This allows the CMP process to achieve planarization in critical areas while maintaining easier embedding conditions in other regions, thus resolving the contradiction between planarization quality and embedding ease.
Solution Approach 2:
The patent employs beforehand cushioning by pre-forming recesses in regions that will undergo CMP processing. These recesses act as a cushioning structure that prevents excessive polishing pressure on high aspect ratio patterns, thereby reducing dishing and void formation while still achieving the desired planarization effect.
3Manufacturing precision
If additional lithography processes are added to form recesses, then planarization and embedding are improved, but device complexity increases
Solution Approach 1:
The patent merges the recess formation process with the existing lithography process used for wiring pattern formation. By combining these processes, the patent achieves improved embedding quality and planarization without adding separate lithography steps, thus avoiding increased device complexity while still obtaining the benefits of selective recess formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances planarization by minimizing dishing and void formation, improving connection reliability and reducing the risk of leaks or short circuits, while allowing for efficient embedding without additional lithography processes.
Implementation Method 1
In order to secure planarization of CMP (chemical mechanical polishing)
Data Source
AI summary
A semiconductor device according to the present embodiment includes a wiring layer including a plurality of wires. The wires include first wires and second wires. Each of the first wires has a first width in a direction substantially parallel to the wiring layer. The second wires are arranged at wider intervals than intervals of the first wires. Each of the second wires includes a first wiring member having a second width larger than the first width, and a second wiring member provided on the first wiring member and having a third width larger than the second width.