Semiconductor Wiring Layout for Short-Circuit-Prone Conductive Plugs
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Solution Overview
Problem
The challenge of short-circuiting conductive plugs in the peripheral region of semiconductor structures due to high-density integration, which causes damage to devices, is exacerbated by the increased height difference and reduced pitch between conductive plugs.
Innovation Solution
A semiconductor structure design with a first wiring layer and first conductive plug that includes multiple sub-layers, where the first wiring layer is positioned below the capacitor structures, and a second wiring layer and second conductive plug that connects to the capacitor structures, reducing the density and length of conductive plugs, and a method for fabricating this structure that forms the wiring layers and plugs in a way that avoids excessive height differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive plugs are formed to penetrate through thicker dielectric layer in peripheral region to achieve electrical connection, then electrical connection is established, but the reduced pitch between conductive plugs causes short-circuiting
Solution Approach 1:
The conductive plug formation process is segmented into multiple stages with different dielectric layers (first dielectric layer 401, second dielectric layer 402) and corresponding conductive plugs (first conductive plugs 202, second conductive plugs 302). This segmentation allows different regions to have optimized plug configurations, preventing short-circuits while maintaining electrical connection.
Solution Approach 2:
Different dielectric layers are applied to different regions: the first dielectric layer covers the peripheral region where shorter conductive plugs are needed, while the second dielectric layer covers the array region. This local quality approach ensures each region has the appropriate dielectric thickness for its specific requirements, preventing short-circuits in the peripheral region.
2Productivity
If high-density integration is implemented to increase memory capacity, then integration density is improved, but the pitch between conductive plugs is reduced causing short-circuit risk
Solution Approach 1:
The patent applies different dielectric layer configurations to different regions based on their specific requirements. The peripheral region receives the first dielectric layer optimized for shorter conductive plugs and higher density integration, while the array region receives the second dielectric layer. This local quality approach enables high-density integration in the peripheral region without causing short-circuits.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating multiple stacked dielectric layers (first dielectric layer 401, second dielectric layer 402) with different heights. This dimensional approach allows the peripheral region to have effectively reduced dielectric thickness for conductive plug formation, enabling higher integration density without compromising reliability.
3Reliability
If capacitor structures with larger height are formed to improve charge storage efficiency, then charge storage efficiency is improved, but the height difference between capacitor structures and peripheral device structures increases
Solution Approach 1:
The dielectric structure is segmented into multiple layers (first dielectric layer 401, second dielectric layer 402) with different heights. The first dielectric layer extends across both peripheral and array regions, while the second dielectric layer is positioned above the array region. This segmentation allows capacitor structures to achieve greater height for improved charge storage efficiency while the first dielectric layer provides a baseline that manages the height difference with peripheral device structures.
Data Source
AI summary
Embodiments provide a semiconductor structure and a fabricating method. The structure includes: a substrate including a capacitor structure and a peripheral device structure; a first wiring layer including a first wiring sub-layer and a second wiring sub-layer, a first conductive plug including a first conductive sub-plug and a second conductive sub-plug, where the first wiring sub-layer is positioned above the peripheral device structure, a terminal of the first conductive sub-plug is electrically connected to the first wiring sub-layer, other terminal of the first conductive sub-plug is electrically connected to the peripheral device structure, the second wiring sub-layer is positioned above the first wiring sub-layer, a terminal of the second conductive sub-plug is electrically connected to the second wiring sub-layer, and other terminal of the second conductive sub-plug is electrically connected to the first wiring sub-layer or the peripheral device structure; and a second wiring layer positioned above the capacitor structure.