Semiconductor Wiring Layout via Contact Conductor Alignment

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Solution Overview

Problem

In semiconductor devices with multi-layered wiring structures, contact conductors connecting wiring layers two or more layers apart restrict the layout of intermediate wiring layers, creating prohibited areas that limit wiring density and flexibility.

Innovation Solution

The semiconductor device and designing method involve forming protrusions and notched portions in the upper and lower wiring layers, allowing contact conductors to be aligned in a single direction, thereby reducing the size of prohibited areas in intermediate layers and enhancing layout flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact conductors connect wiring layers two or more layers apart, then power line connectivity is improved, but prohibited areas in intermediate wiring layers increase

Engineering Contradiction:
Improvepower line connectivityVSAvoidprohibited area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent aligns contact conductors in the first direction (parallel arrangement) rather than allowing diagonal placement, effectively changing the dimensional arrangement from 2D diagonal positioning to 1D linear positioning. This dimensional simplification reduces the prohibited area width in intermediate wiring layers while maintaining power line connectivity across multiple layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameter of contact conductor arrangement from diagonal/ scattered positioning to parallel alignment in a specific direction. This parameter change (arrangement orientation and spacing) directly reduces the prohibited area width in intermediate layers while preserving the electrical connectivity function.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If contact conductors are arranged diagonally to connect wirings, then connectivity flexibility is improved, but prohibited area width increases

Engineering Contradiction:
Improveconnectivity flexibilityVSAvoidprohibited area width
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from diagonal 2D arrangement to parallel 1D arrangement of contact conductors, reducing the prohibited area width while maintaining connectivity through the first direction alignment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces asymmetric arrangement where contact conductors are deliberately aligned in the first direction rather than symmetrically distributed, creating an optimized pattern that reduces prohibited area while maintaining necessary connectivity.

Inventive Principle:
Principle #4Asymmetry

3Productivity

If wiring density in each wiring layer is increased, then circuit functionality is improved, but layout restrictions from contact conductors worsen

Engineering Contradiction:
Improvewiring densityVSAvoidlayout flexibility
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

By aligning contact conductors in the first direction, the patent reduces the prohibited area width, thereby increasing the available area for wiring layout in intermediate layers and enabling higher wiring density without compromising layout flexibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the contact conductor arrangement parameters (alignment direction and spacing) to minimize prohibited area, which directly increases the usable wiring area and allows for higher wiring density while maintaining layout ease.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8823173B2Semiconductor device having plurality of wiring layers and designing method thereof
Publication Date: 2014.09.02 LONGITUDE LICENSING LTD
  • US8823173B2 patent drawing
  • US8823173B2 patent drawing
  • US8823173B2 patent drawing

AI summary

A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower.