Semiconductor Device Multi-Layer Wiring Crosstalk Reduction
Solution Overview
Problem
The challenge is to enhance the transmission speed of signals in semiconductor devices while minimizing noise interference between high-density signal transmission paths, which is crucial for maintaining high-speed data transfer without increasing the device size.
Innovation Solution
The solution involves arranging signal wirings for input and output in different layers of the wiring substrate, with conductor patterns supplied with fixed potential sandwiching these wirings, and positioning signal electrodes in specific rows on the semiconductor chip to reduce crosstalk noise and allow for a higher packing density of transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal transmission paths are arranged at high density in proximity to input/output terminals, then the number of high-speed transmission paths increases, but mutual noise interference between transmission paths increases
Solution Approach 1:
The patent applies three-dimensional wiring technology to arrange signal transmission paths in multiple layers (first wiring layer and second wiring layer) rather than solely in a planar configuration. This vertical stacking allows increased transmission path density while maintaining spatial separation between paths, thereby reducing mutual noise interference while increasing the number of available high-speed transmission paths
Solution Approach 2:
The patent segments signal transmission paths into different wiring layers, with signal wirings in the first layer and ground wirings in the second layer. This segmentation separates signal carrying functions from ground reference functions into distinct layers, reducing electromagnetic coupling and noise interference between adjacent transmission paths while enabling higher path density
2Device complexity
If signal wirings for input and output are disposed in the same wiring layer, then wiring layout is simplified, but crosstalk noise between input and output signals increases
Solution Approach 1:
The patent transitions from two-dimensional planar wiring arrangement to three-dimensional multi-layer wiring configuration. Signal wirings for input and output are disposed in different wiring layers (first and second wiring layers respectively), utilizing the vertical dimension to separate signal paths. This reduces crosstalk noise between input and output signals while the layered structure maintains relatively simple wiring layout through systematic layer assignment
3Volume of moving object
If the thickness of the wiring substrate is reduced to minimize device size, then device compactness increases, but signal transmission quality deteriorates due to increased susceptibility to noise
Solution Approach 1:
The patent implements a nested structure where ground wirings are positioned adjacent to and surrounding signal wirings in different wiring layers. The ground wirings act as a protective enclosure for the signal wirings, creating a shielded transmission path configuration. This nested arrangement provides effective noise shielding while maintaining compact device dimensions, as the ground wirings are integrated into the same multi-layer structure rather than requiring additional external shielding elements
Data Source
AI summary
A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.