Semiconductor Wiring Penetration Passages for Cleaner Cu Etching
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Solution Overview
Problem
In semiconductor device manufacturing, the narrow intervals between wiring patterns lead to poor etching rates due to accumulation of residual dissolution material, causing Cu residue and defects such as excessively narrow wiring widths.
Innovation Solution
The introduction of penetration passages within the wiring structure that allow etching fluids to flow through, formed by linear mask components with features narrower than the exposure device's resolution limit, preventing residual material accumulation and improving etching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If narrow intervals between wiring patterns are used to increase integration density, then area utilization is improved, but etching performance deteriorates due to accumulation of residual dissolution material
Solution Approach 1:
The patent introduces penetration passages that divide the continuous wiring structure into segmented regions, allowing etching fluid to access and remove dissolution material from previously unreachable areas between adjacent wiring patterns
Solution Approach 2:
The patent adds a vertical dimension solution by creating penetration passages through the wiring thickness, enabling etching fluid to flow from the top surface down into the narrow intervals between wiring patterns, thus solving the 2D planar limitation
2Manufacturing precision
If prolonged etching is performed to remove Cu residue, then cleanliness is improved, but wiring width is reduced due to over-etching
Solution Approach 1:
The patent performs preliminary cleaning action by introducing penetration passages that enable complete removal of dissolution material during the main etching process, eliminating the need for prolonged additional etching that would cause over-etching
3Reliability
If Cu seed layer is used to ensure adhesive strength, then reliability is improved, but etching difficulty increases due to Cu residue formation
Solution Approach 1:
The patent extracts the problematic Cu residue by enabling complete removal through penetration passages, separating the adhesive function from the etching difficulty issue
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances etching performance by ensuring fluid circulation through narrow spaces, reducing Cu residue accumulation and preventing defects like excessively narrow wiring widths, thereby maintaining reliable adhesive properties and structural integrity.
Implementation Method 1
removal of the Cu seed layer is performed using wet etching
Implementation Method 2
The wiring is then formed, for example, by depositing copper using an electroplating method
Data Source
AI summary
A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.