Semiconductor Wiring Patterns with Cut Portions for Area Reduction
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Solution Overview
Problem
The existing semiconductor manufacturing processes using sidewall transfer techniques face challenges in minimizing the chip area required for forming fine wiring patterns, leading to increased area usage due to the formation of multiple loops around mandrels during the patterning process.
Innovation Solution
The proposed solution involves a semiconductor device with a wiring pattern comprising parallel conductive lines that include cut portions, where the sidewall transfer technique is used twice to form a three-cut pattern, reducing the area required by cutting three adjacent wiring patterns and utilizing dummy lines for improved dielectric breakdown voltage and reduced shorting risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the sidewall transfer technique is used to form fine wiring patterns, then the manufacturing precision is improved, but the chip area increases due to multiple loops around mandrels
Solution Approach 1:
The patent applies segmentation by dividing the continuous wiring pattern into multiple segments with cut portions. The first and second wiring patterns are separated by a cut portion, and each pattern is further divided into multiple lines (first, second, third lines) with intermediate cut portions. This segmentation eliminates the need for multiple loops around mandrels, thereby reducing chip area while maintaining fine pattern precision through the sidewall transfer technique.
2Quantity of substance
If the number of wirings formed in a loop shape around the mandrel is increased, then the area to be cut is increased, but this leads to increased chip area usage
Solution Approach 1:
The patent extracts the unnecessary loop portions by introducing cut portions that remove the need for wirings to loop around mandrels. The first wiring pattern has a cut portion that eliminates the loop, and the second wiring pattern is similarly optimized. This extraction reduces the area to be cut and minimizes chip area usage while maintaining the required number of wirings for functional integrity.
3Area of stationary object
If cut patterns are formed to reduce chip area, then the area usage is minimized, but the risk of shorting between bit lines and wiring patterns increases
Solution Approach 1:
The patent applies local quality by strategically positioning cut portions and dummy lines in specific locations to address shorting risks. The cut portions are placed at critical areas where bit lines and wiring patterns might intersect, and dummy lines are added in specific positions to maintain dielectric breakdown voltage. This localized optimization reduces shorting risk while maintaining minimal chip area usage.
Solution Approach 2:
The patent implements preliminary action by forming dummy lines in advance before final wiring pattern completion. These dummy lines are positioned to prevent shorting between bit lines and wiring patterns, and they maintain the dielectric breakdown voltage required for reliable operation. This preliminary structural preparation ensures reliability is built into the design before manufacturing constraints are finalized.
Data Source
AI summary
A semiconductor device includes a plurality of parallel conductive lines that are spaced apart from one another in a first direction and extend in a second direction transverse to the first direction. The parallel conductive lines includes first and second lines that are adjacent, and a third line that is adjacent to the second line, and the first and third lines each have a cut portion at different points along the second direction.