Semiconductor Wiring Film Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in simultaneously patterning bit lines in a cell array region and peripheral gates in a peripheral circuit region without causing pitting phenomena due to differences in etching amounts, which can lead to increased parasitic capacitance when attempting to prevent pitting by thickening the peripheral gate film.
Innovation Solution
The method involves forming a semiconductor device by preparing a substrate with a cell array and peripheral circuit region, using an etching buffer film, such as lanthanum or lanthanum oxide, to selectively expose the etching buffer film and wiring films, allowing for the simultaneous patterning of bit lines and peripheral gates while minimizing the thickness of the wiring films and thus reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the film for forming the peripheral gate is increased to prevent the pitting phenomenon, then the pitting phenomenon is prevented, but the parasitic capacitance increases
Solution Approach 1:
The patent divides the film structure into multiple segments: a first wiring film layer and a second wiring film layer with different thicknesses. The first wiring film in the peripheral circuit region is made thinner to reduce parasitic capacitance, while the second wiring film maintains sufficient thickness to prevent pitting. This segmentation allows different regions to have optimized film thicknesses for their specific functional requirements.
Solution Approach 2:
The patent applies different film thickness characteristics to different regions: the first wiring film in the peripheral circuit region has a first thickness optimized for low parasitic capacitance, while the second wiring film has a second thickness optimized for pitting prevention. This local quality approach ensures that each region has the precise film thickness needed for its specific operational requirements without compromising overall device performance.
2Loss of energy
If the thickness of the first wiring film is reduced to decrease parasitic capacitance, then parasitic capacitance is reduced, but the pitting phenomenon occurs in the peripheral circuit region
Solution Approach 1:
The patent segments the wiring film into two distinct layers with different thickness profiles. The first wiring film layer is made thinner in the peripheral circuit region to reduce parasitic capacitance, while the second wiring film layer provides additional thickness to prevent pitting. This segmentation resolves the contradiction by distributing the thickness requirements across different layers.
Solution Approach 2:
The patent uses a composite structure consisting of multiple wiring film layers with different material compositions and thicknesses. The first wiring film and second wiring film are formed as a composite system where each layer contributes different properties: the first layer minimizes capacitance while the second layer prevents pitting, achieving both goals simultaneously through material composition design.
Data Source
AI summary
Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.