Semiconductor Wiring Grain Size Optimization
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the planar area occupied by wiring structures and peripheral circuits for three-dimensional memory cells, which hinders the integration and efficiency of next-generation memory devices like PRAM and RRAM.
Innovation Solution
The semiconductor device incorporates a peripheral wiring structure with a lower wiring structure and an upper wiring structure, where the upper wiring structure has a second material layer with smaller grains compared to the first material layer in the lower wiring structure, optimizing the grain size and seam size to minimize the infiltration of insulating materials and enhance connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the planar area of wiring structures is reduced to increase integration density, then the degree of integration is improved, but the reliability of wiring connections deteriorates due to increased risk of insulating material infiltration and reduced wiring robustness
Solution Approach 1:
The patent applies local quality by using different grain sizes in different wiring layers. The upper wiring structure has smaller grains while the lower wiring structure has larger grains. This local differentiation optimizes each layer for its specific function: smaller grains in upper layers prevent insulating material infiltration and improve connection reliability, while larger grains in lower layers maintain structural robustness. This resolves the contradiction by allowing high integration density through optimized upper wiring while maintaining reliability through differentiated local properties.
Solution Approach 2:
The patent employs composite materials by combining material layers with different grain structures within the wiring system. The upper wiring uses a material layer with fine grains (average size 1-10 nm) while the lower wiring uses a material layer with coarser grains (average size 10-100 nm). This composite approach allows the system to achieve both high integration density and reliable connections by leveraging the complementary properties of different material structures in different spatial locations.
2Reliability
If the grain size of wiring material is reduced to prevent insulating material infiltration, then the reliability is improved, but the manufacturing complexity increases due to precise control requirements
Solution Approach 1:
The patent implements local quality by specifying different grain size ranges for different wiring layers. The upper wiring structure uses material with smaller grains (1-10 nm average size) to prevent insulating material infiltration, while the lower wiring structure uses material with larger grains (10-100 nm average size) that are easier to manufacture. This local differentiation achieves high reliability where needed without requiring ultra-fine grain control throughout the entire wiring system, thus reducing overall manufacturing complexity.
Solution Approach 2:
The patent applies segmentation by dividing the wiring system into distinct layers with different grain size requirements. The upper wiring layer is segmented from the lower wiring layer, each with optimized grain structures suited to their specific functional requirements. This segmentation allows independent optimization of each layer's grain size, making the manufacturing process more manageable by focusing precise control only where necessary (upper layer) while using standard processes for other layers.
3Strength
If the grain size of wiring material is increased to improve structural robustness, then the strength is improved, but the infiltration resistance of insulating materials deteriorates
Solution Approach 1:
The patent applies local quality by assigning different grain sizes to different wiring layers based on their specific functional requirements. The upper wiring structure, which is more susceptible to insulating material infiltration, uses smaller grains (1-10 nm average size) to block infiltration paths. The lower wiring structure, which requires greater structural robustness, uses larger grains (10-100 nm average size). This local differentiation resolves the contradiction by providing infiltration resistance where needed and structural strength where needed, without requiring a compromise that would weaken either property throughout the entire system.
Data Source
AI summary
A semiconductor device including a semiconductor substrate; a memory cell structure on the semiconductor substrate; and a peripheral wiring structure between the semiconductor substrate and the memory cell structure to connect the semiconductor substrate and the memory cell structure, wherein the peripheral wiring structure includes at least one lower wiring structure and an upper wiring structure on the at least one lower wiring structure, the at least one lower wiring structure includes a lower wiring, the upper wiring structure includes an upper wiring, the lower wiring includes a first material layer having first grains, the upper wiring includes a second material layer having second grains, an average size of the second grains is smaller than an average size of the first grains.