Semiconductor Wiring Stack With Groove-Filled Interconnect Joining
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Solution Overview
Problem
Existing semiconductor manufacturing methods require multiple redistribution layers to match bump or pad diameters, leading to reduced productivity, insufficient miniaturization, and potential deformation of solder connections, which can affect yield and insulation reliability.
Innovation Solution
A method involving the formation of conductive layers in grooves of organic insulating layers, followed by precise alignment and stacking with barrier metal films to prevent diffusion and ensure reliable joining of wiring layers, allowing for fine and dense wiring structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple redistribution layers are used to match bump or pad diameters, then connection compatibility is improved, but productivity deteriorates and device complexity increases
Solution Approach 1:
The patent extracts the diameter-matching function from the redistribution layers and transfers it to the groove structure. The grooves are formed with specific dimensions to directly accommodate bumps or pads of different diameters, eliminating the need for multiple redistribution layers and their associated complex manufacturing processes.
Solution Approach 2:
The patent transitions from a planar wiring layer approach to a three-dimensional groove-based approach. By forming grooves with controlled depth and width, the system achieves diameter matching in the vertical dimension rather than relying on multiple horizontal wiring layers, thereby reducing overall device complexity.
2Adaptability or versatility
If multiple redistribution layers are used to match bump or pad diameters, then connection compatibility is improved, but miniaturization capability deteriorates
Solution Approach 1:
The patent removes the bulky multiple redistribution layer structure and replaces it with a compact groove-based system. The grooves are formed directly in the substrate or support member, eliminating the need for additional wiring layers and reducing overall device volume.
Solution Approach 2:
The patent utilizes the vertical dimension by forming grooves with controlled depth, allowing diameter matching without adding horizontal wiring layers. This three-dimensional approach enables miniaturization while maintaining the ability to accommodate different bump or pad diameters.
3Strength
If solder is melted by heating and pressurization to stack semiconductor chips, then connection strength is improved, but solder deformation occurs and yield ratio deteriorates
Solution Approach 1:
The patent performs preliminary actions by pre-forming grooves with precise dimensions and providing barrier metal films before chip stacking. The grooves are designed to guide and constrain the solder or conductive material, preventing deformation during the heating and pressurization process while maintaining connection strength.
Solution Approach 2:
The patent introduces barrier metal films as intermediary layers between the substrate/support member and the solder or conductive material. These barrier films prevent diffusion and provide a controlled interface that maintains positioning accuracy during the bonding process while ensuring strong connections.
4Quantity of substance
If distance between solder and solder is shortened to achieve high density, then high density is improved, but insulation reliability deteriorates
Solution Approach 1:
The patent applies local quality by providing barrier metal films specifically at the interfaces where solder or conductive material contacts the substrate or support member. This localized treatment prevents diffusion and maintains insulation reliability even when the distance between adjacent solder elements is reduced for high-density configurations.
Data Source
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Figure 3A~3D
AI summary
A method for manufacturing a semiconductor device includes forming a first organic insulating layer including a groove on a substrate; forming a conductive layer formed from a conductive material on the first organic insulating layer so as to fill the groove with the conductive material; removing a portion of the conductive layer on the first organic insulating layer, and acquiring a first wiring structure including a first wiring layer including the conductive material filled in the groove, and the first organic insulating layer; providing a second wiring structure including a second organic insulating layer and a second wiring layer; and stacking the first wiring structure and the second wiring structure by pressurizing them each other while performing alignment so that the first wiring layer and the second wiring layer correspond to each other. In the stacking, the first wiring layer and the second wiring layer are joined, and the first organic insulating layer and the second organic insulating layer are joined to each other.